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? 2011-2015 microchip technology inc. ds40001458d-page 1 high-performance risc cpu c compiler optimized architecture only 49 instructions operating speed: - dc C 20 mhz clock input @ 2.5v - dc C 16 mhz clock input @ 1.8v - dc C 200 ns instruction cycle interrupt capability with automatic context saving 16-level deep hardware stack with optional overflow/underflow reset direct, indirect and relative addressing modes: - two full 16-bit file select registers (fsrs) - fsrs can read program and data memory memory up to 28 kbytes linear program memory addressing up to 1536 bytes linear data memory addressing high-endurance flash data memory (hef) - 128b of nonvolatile data storage - 100k erase/write cycles flexible oscillator structure 16 mhz internal oscillator block: - software selectable frequency range from 16 mhz to 31 khz 31 khz low-power internal oscillator external oscillator block with: - four crystal/resonator modes up to 20 mhz - three external clock modes up to 20 mhz fail-safe clock monitor - allows safe shutdown if peripheral clock stops two-speed oscillator start-up oscillator start-up timer (ost) special microcontroller features operating voltage range: - 1.8v to 3.6v (pic16lf1526/7) - 2.3v to 5.5v (pic16f1526/7) self-programmable under software control power-on reset (por) power-up timer (pwrt) programmable low-power brown-out reset (lpbor) extended watch-dog timer (wdt): - programmable period from 1 ms to 256s programmable code protection in-circuit serial programming? (icsp?) via two pins in-circuit debug (icd) via two pins enhanced low-voltage programming (lvp) power-saving sleep mode extreme low-power management pic16lf1526/7 with xlp sleep mode: 20 na @ 1.8v, typical watchdog timer: 300 na @ 1.8v, typical secondary oscillator: 600 na @ 32 khz, 1.8v, typical analog features analog-to-digital converter (adc): - 10-bit resolution - 30 external channels - two internal channels - fixed voltage reference (fvr) channel - temperature indicator channel - auto acquisition capability - conversion available during sleep - dedicated adc rc oscillator - fixed voltage reference (fvr) as adc positive reference voltage reference module: - fixed voltage reference (fvr) with 1.024v, 2.048v and 4.096v output levels - low-power sleep mode - low-power bor (lpbor) peripheral features 53 i/o pins and one input-only pin: - high current sink/source 25 ma/25 ma - individually programmable weak pull-ups - individually programmable interrupt-on-change (ioc) pins timer0: 8-bit timer/counter with 8-bit programmable prescaler enhanced timer1, 3, 5: - 16-bit timer/counter with prescaler - external gate input mode - low-power 32 khz secondary oscillator driver timer2, 4, 6, 8, 10: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ten capture/compare/pwm (ccp) modules: - 16-bit capture, 200 ns (max. resolution) - 16-bit compare, 200 ns (max. resolution) - 10-bit pwm, 20 khz @ 10 bits (max. frequency) two master synchronous serial ports (mssps) with spi and i 2 c tm with: - 7-bit address masking - smbus/pmbus tm compatibility - auto-wake-up on start two enhanced universal synchronous asynchronous receiver transmitters (eusart): - rs-232, rs-485 and lin compatible - auto-baud detect pic16(l)f1526/7 64-pin flash microcontrollers with xlp technology downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 2 ? 2011-2015 microchip technology inc. pic16(l)f151x/152x family types device data sheet index program memory flash (words) data sram (bytes) high-endurance flash (bytes) i/o?s (2) adc timers (8/16-bit) eusart mssp (i 2 c/spi) ccp debug (1) xlp 10-bit (ch) advanced control pic16(l)f1512 (1) 2048 128 128 25 17 y 2/1 1 1 2 i y pic16(l)f1513 (1) 4096 256 128 25 17 y 2/1 1 1 2 i y pic16(l)f1516 (2) 8192 512 128 25 17 n 2/1 1 1 2 i y pic16(l)f1517 (2) 8192 512 128 36 28 n 2/1 1 1 2 i y pic16(l)f1518 (2) 16384 1024 128 25 17 n 2/1 1 1 2 i y pic16(l)f1519 (2) 16384 1024 128 36 28 n 2/1 1 1 2 i y pic16(l)f1526 (3) 8192 768 128 54 30 n 6/3 2 2 10 i y pic16(l)f1527 (3) 16384 1536 128 54 30 n 6/3 2 2 10 i y note 1: i - debugging, integrated on chip; h - debugging, available using debug header. 2: one pin is input-only. data sheet index: (unshaded devices are described in this document.) 1: ds41624 pic16(l)f1512/13 data sheet, 28-pin flash, 8-bit microcontrollers. 2: ds41452 pic16(l)f1516/7/8/9 data sheet, 28/40/44-pin flash, 8-bit mcus. 3: ds41458 pic16(l)f1526/7 data sheet, 64-pin flash, 8-bit mcus. note: for other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 3 pic16(l)f1526/7 figure 1: 64-pin tqfp (10mm x 10mm) package diagram for pic16(l)f1526/7 12 3 4 5 6 7 8 9 10 11 12 13 14 3837 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 re2 re3 re4 re5 re6 re7 rd0 v dd v ss rd1 rd2 rd3 rd4 rd5 rd6 rd7 re1 re0 rg0rg1 rg2 rg3 v pp /mclr /rg5 rg4 v ss v dd rf7 rf6 rf5 rf4 rf3 rf2 rb0 rb1 rb2 rb3 rb4 rb5 rb6 v ss ra6 ra7 v dd rb7 rc4 rc3 rc2 rf0 rf1 av dd av ss ra3 ra2 ra1 ra0 v ss v dd ra4 ra5 rc1rc0 rc7 rc6 rc5 1516 31 4039 27 28 29 30 32 4847 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 note 1: see table 1 for list of pin peripheral function. pic16(l)f1526 pic16(l)f1527 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 4 ? 2011-2015 microchip technology inc. figure 2: 64-pin qfn (9mm x 9mm) p ackage diagram for pic16(l)f1526/7 12 3 4 5 6 7 8 9 10 11 12 13 14 3837 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 re2 re3 re4 re5 re6 re7 rd0 v dd v ss rd1rd2 rd3 rd4 rd5 rd6 rd7 re1 re0 rg0 rg1 rg2 rg3 v pp /mclr /rg5 rg4 v ss v dd rf7 rf6 rf5 rf4 rf3 rf2 rb0 rb1 rb2 rb3 rb4 rb5 rb6 v ss ra6 ra7 v dd rb7 rc4 rc3 rc2 rf0 rf1 av dd av ss ra3 ra2 ra1 ra0 v ss v dd ra4 ra5 rc1rc0 rc7 rc6 rc5 1516 31 4039 27 28 29 30 32 4847 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 pic16(l)f1526 pic16(l)f1527 note 1: see table 1 for list of pin peripheral function. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 5 pic16(l)f1526/7 table 1: 64-pin device allocat ion table (pic16(l)f1526/7) i/o 64-pin tqfp, qfn adc timers ccp usart ssp interrupt pull-up basic ra0 24 an0 ra1 23 an1 ra2 22 an2 ra3 21 an3 v ref + ra4 28 t0cki ra5 27 an4 t3g ra6 40 osc2/clkout ra7 39 osc1/clkin rb0 48 an17 int/ ioc y rb1 47 an18 ioc y rb2 46 an19 ioc y rb3 45 an20 ioc y rb4 44 an21 t3cki (1) ioc y rb5 43 an22 t1g/t3cki ioc y rb6 42 ioc y icspclk/icdclk rb7 37 ioc y icspdat/icddat rc0 30 sosco/t1cki rc1 29 sosci ccp2 rc2 33 ccp1 rc3 34 sck1/scl1 rc4 35 sdi1/sda1 rc5 36 sdo1 rc6 31 tx1/ck1 rc7 32 rx1/dt1 rd0 58 an23 y rd1 55 an24 t5cki y rd2 54 an25 y rd3 53 an26 y rd4 52 sdo2 y rd5 51 sdi2, sda2 y rd6 50 sck2, scl2 y rd7 49 ss2 y re0 2 an27 y re1 1 an28 y re2 64 an29 ccp10 y re3 63 ccp9 y re4 62 ccp8 y re5 61 ccp7 y re6 60 ccp6 y note 1: alternate pin function selected with the apfcon ( register 12-1 ) register. 2: weak pull-up is always enabled when mclr is enabled, otherwise the pull-up is under user control. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 6 ? 2011-2015 microchip technology inc. table 1: 64-pin device allocation table (pic16(l)f1526/7) (continued) i/o 64-pin tqfp, qfn adc timers ccp usart ssp interrupt pull-up basic re7 59 ccp2 (1) y rf0 18 an16 v cap rf1 17 an6 rf2 16 an7 rf3 15 an8 rf4 14 an9 rf5 13 an10 rf6 12 an11 rf7 11 an5 ss1 rg0 3 ccp3 rg1 4 an15 tx2/ck2 rg2 5 an14 rx2/dt2 rg3 6 an13 ccp4 rg4 8 an12 t5g ccp5 rg5 7 y (2) mclr /v pp v dd 10, 26, 38, 57 v dd v ss 9, 25, 41, 56 v ss av dd 19 av dd av ss 20 av ss note 1: alternate pin function selected with the apfcon ( register 12-1 ) register. 2: weak pull-up is always enabled when mclr is enabled, otherwise the pull-up is under user control. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 7 pic16(l)f1526/7 table of contents 1.0 device overview ....................................................... ...................................................... ............................................................. 9 2.0 enhanced mid-range cpu ........................................... ................................................... ........ .................................................. 15 3.0 memory organization .......................................... ................................................... ............ ........................................................ 17 4.0 device configuration .................................................................. ...................................... .......................................................... 42 5.0 oscillator module (with fail-safe clock monitor)........................................................... ................. ........................................... 48 6.0 resets .......................................................................................... .............................................................................................. 63 7.0 interrupts .................................................................................... ................................................................................................ 71 8.0 power-down mode (sleep) .............................................. ................................................... .... ................................................... 86 9.0 low dropout (ldo) voltage regulator ....................................... .................................................. ............................................. 90 10.0 watchdog timer (wdt) ........................................ ................................................... ............ ...................................................... 91 11.0 flash program memory control ................................................... ............................................ .................................................. 95 12.0 i/o ports ....................................................................................... ........................... ................................................................. 111 13.0 interrupt-on-change ............................................ ................................................... ......... ......................................................... 135 14.0 fixed voltage reference (fvr) ...................................... ................................................... ..... ................................................. 139 15.0 temperature indicator module ......................................... ................................................... ... .................................................. 141 16.0 analog-to-digital converter (adc) module ..................................... .............................................. ........................................... 143 17.0 timer0 module .............................................. ................................................... ............. ........................................................... 156 18.0 timer1/3/5 modules............................................ ................................................... .......... ......................................................... 159 19.0 timer2/4/6/8/10 modules...................................................... .............................................. ...................................................... 171 20.0 capture/compare/pwm module ........................................ ................................................... ...... ............................................. 175 21.0 master synchronous serial port (mssp) module ................................. .............................................. ..................................... 193 22.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) ....................................... ........... ............. 248 23.0 in-circuit serial programming ? (icsp ? ) ......................................................................................................... ....................... 278 24.0 instruction set summary ........................................................ ............................................ ...................................................... 280 25.0 electrical specifications................................................... ............................................... .......................................................... 294 26.0 dc and ac characteristics graphs and tables................................... ............................................. ....................................... 324 27.0 development support............................................ ................................................... ......... ....................................................... 358 28.0 packaging information..................................................... ................................................. ........................................................ 362 appendix a: revision history.......................................... ................................................... ...... .......................................................... 369 the microchip web site ....................................................................... .................................. ............................................................ 371 customer change notification service ....................................... ................................................... . ................................................... 371 customer support............................................... ................................................... ............. ............................................................... 371 product identification system ................................................. ..................................................................................................... ...... 370 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 8 ? 2011-2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 9 pic16(l)f1526/7 1.0 device overview the pic16(l)f1526/7 are described within this data sheet. they are available in 64-pin packages. figure 1-1 shows a block diagram of the pic16(l)f1526/7 devices. table 1-2 shows the pinout descriptions. reference tab l e 1 - 1 for peripherals available per device. table 1-1: device peripheral summary peripheral pic16f1526 pic16lf1526 pic16f1527 pic16lf1527 adc eusart fixed voltage reference (fvr) temperature indicator capture/compare/pwm modules ccp1 ccp2 ccp3 ccp4 ccp5 ccp6 ccp7 ccp8 ccp9 ccp10 eusarts eusart1 eusart2 master synchronous serial ports mssp1 mssp2 timers timer0 timer1/3/5 timer2/4/6 /8/10 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 10 ? 2011-2015 microchip technology inc. figure 1-1: pic16(l)f1526/7 block diagram mssps timer2/4/6/8/10 timer1/3/5 ccp1-10 eusarts timer0 note 1: see applicable chapters for more information on peripherals. 2: see ta b l e 1 - 1 for peripherals available on specific devices. cpu program flash memory ram timing generation intrc oscillator mclr ( figure 2-1 ) osc1/clkin osc2/clkout adc 10-bit fvr te m p . indicator portb porta portc portd porte portf portg downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 11 pic16(l)f1526/7 table 1-2: pic16(l)f1526/7 pinout description name function input type output type description ra0/an0 ra0 ttl cmos general purpose i/o. an0 an adc channel 0 input. ra1/an1 ra1 ttl cmos general purpose i/o. an1 an adc channel 1 input. ra2/an2 ra2 ttl cmos general purpose i/o. an2 an adc channel 2 input. ra3/an3/v ref + ra3 ttl cmos general purpose i/o. an3 an adc channel 3 input. v ref + an adc positive voltage reference input. ra4/t0cki ra4 ttl cmos general purpose i/o. t0cki st timer0 clock input. ra5/an4/t3g ra5 ttl cmos general purpose i/o. an4 an adc channel 4 input. t3g st timer3 gate input. ra6/osc2/clkout ra6 ttl cmos general purpose i/o. osc2 xtal crystal/resonator (lp, xt, hs modes). clkout cmos f osc /4 output. ra7/osc1/clkin ra7 ttl cmos general purpose i/o. osc1 xtal crystal/resonator (lp, xt, hs modes). clkin st external clock input (ec mode). rb0/an17/int rb0 ttl cmos general purpose i/o with ioc and wpu. an17 an adc channel 17 input. int st external interrupt. rb1/an18 rb1 ttl cmos general purpose i/o with ioc and wpu. an18 an adc channel 18 input. rb2/an19 rb2 ttl cmos general purpose i/o with ioc and wpu. an19 an adc channel 19 input. rb3/an20 rb3 ttl cmos general purpose i/o with ioc and wpu. an20 an adc channel 20 input. rb4/an21/t3cki (1) rb4 ttl cmos general purpose i/o with ioc and wpu. an21 an adc channel 21 input. t3cki st timer3 clock input. rb5/an22/t1g/t3cki rb5 ttl cmos general purpose i/o with ioc and wpu. an22 an adc channel 22 input. t1g st timer1 gate input. t3cki st timer3 clock input. rb6/icspclk/icdclk rb6 ttl cmos general purpose i/o with ioc and wpu. icspclk st serial programming clock. icdclk st in-circuit debug clock. rb7/icspdat/icddat rb7 ttl cmos general purpose i/o with ioc and wpu. icspdat st cmos icsp? data i/o. icddat st cmos in-circuit data i/o. legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 12-1 ) register. 2: rc3, rc4, rd5 and rd6 read the i 2 c st input when i 2 c mode is enabled. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 12 ? 2011-2015 microchip technology inc. rc0/sosco/t1cki rc0 st cmos general purpose i/o. sosco xtal xtal timer1/3/5 oscillator connection. t1cki st timer1/3/5 clock input. rc1/sosci/ccp2 rc1 st cmos general purpose i/o. sosci xtal xtal timer1/3/5 oscillator connection. ccp2 st cmos capture/compare/pwm2. rc2/ccp1 rc2 st cmos general purpose i/o. ccp1 st cmos capture/compare/pwm1. rc3/sck1/scl1 (2) rc3 st cmos general purpose i/o. sck1 st cmos spi clock. scl1 i 2 co di 2 c clock. rc4/sdi1/sda1 (2) rc4 st cmos general purpose i/o. sdi1 st spi data input. sda1 i 2 co di 2 c data input/output. rc5/sdo1 rc5 st cmos general purpose i/o. sdo1 cmos spi data output. rc6/tx1/ck1 rc6 st cmos general purpose i/o. tx1 cmos usart1 asynchronous transmit. ck1 st cmos usart1 synchronous clock. rc7/rx1/dt1 rc7 st cmos general purpose i/o. rx1 st usart1 asynchronous input. dt1 st cmos usart1 synchronous data. rdo/an23 rd0 st cmos general purpose i/o with wpu. an23 an adc channel 23 input. rd1/an24/t5cki rd1 st cmos general purpose i/o with wpu. an24 an adc channel 24 input. t5cki st timer5 clock input. rd2/an25 rd2 st cmos general purpose i/o with wpu. an25 an adc channel 25 input. rd3/an26 rd3 st cmos general purpose i/o with wpu. an26 an adc channel 26 input. rd4/sdo2 rd4 st cmos general purpose i/o with wpu. sdo2 cmos spi data output. rd5/sdi2/sda2 (2) rd5 st cmos general purpose i/o with wpu. sdi2 st spi data input. sda2 i 2 co di 2 c data input/output. rd6/sck2/scl2 (2) rd6 st cmos general purpose i/o with wpu. sck2 st cmos spi clock. scl2 i 2 co di 2 c clock. rd7/ss2 rd7 st cmos general purpose i/o with wpu. ss2 st slave select input. re0/an27 re0 st cmos general purpose i/o with wpu. an27 an adc channel 27 input. table 1-2: pic16(l)f1526/7 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 12-1 ) register. 2: rc3, rc4, rd5 and rd6 read the i 2 c st input when i 2 c mode is enabled. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 13 pic16(l)f1526/7 re1/an28 re1 st cmos general purpose i/o with wpu. an28 an adc channel 28 input. re2/an29/ccp10 re2 st cmos general purpose i/o with wpu. an29 an adc channel 29 input. ccp10 st cmos capture/compare/pwm10. re3/ccp9 re3 st cmos general purpose i/o with wpu. ccp9 st cmos capture/compare/pwm9. re4/ccp8 re4 st cmos general purpose i/o with wpu. ccp8 st cmos capture/compare/pwm8. re5/ccp7 re5 st cmos general purpose i/o with wpu. ccp7 st cmos capture/compare/pwm7. re6/ccp6 re6 st cmos general purpose i/o with wpu. ccp6 st cmos capture/compare/pwm6. re7/ccp2 (1) re7 st cmos general purpose i/o with wpu. ccp2 st cmos capture/compare/pwm2. rf0/an16/v cap rf0 st cmos general purpose i/o. an16 an adc channel 16 input. v cap power power filter capacitor for voltage regulator. rf1/an6 rf1 st cmos general purpose i/o. an6 an adc channel 6 input. rf2/an7 rf2 st cmos general purpose i/o. an7 an adc channel 7 input. rf3/an8 rf3 st cmos general purpose i/o. an8 an adc channel 8 input. rf4/an9 rf4 st cmos general purpose i/o. an9 an adc channel 9 input. rf5/an10 rf5 st cmos general purpose i/o. an10 an adc channel 10 input. rf6/an11 rf6 st cmos general purpose i/o. an11 an adc channel 11 input. rf7/an5/ss1 rf7 st cmos general purpose i/o. an5 an adc channel 5 input. ss1 st slave select input. rg0/ccp3 rg0 st cmos general purpose i/o. ccp3 st cmos capture/compare/pwm3. rg1/an15/tx2/ck2 rg1 st cmos general purpose i/o. an15 an adc channel 15 input. tx2 cmos usart2 asynchronous transmit. ck2 st cmos usart2 synchronous clock. rg2/an14/rx2/dt2 rg2 st cmos general purpose i/o. an14 an adc channel 14 input. rx2 st usart2 asynchronous input. dt2 st cmos usart2 synchronous data. table 1-2: pic16(l)f1526/7 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 12-1 ) register. 2: rc3, rc4, rd5 and rd6 read the i 2 c st input when i 2 c mode is enabled. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 14 ? 2011-2015 microchip technology inc. rg3/an13/ccp4 rg3 st cmos general purpose i/o. an13 an adc channel 13 input. ccp4 st cmos capture/compare/pwm4. rg4/an12/t5g/ccp5 rg4 st general purpose input. an12 an adc channel 12 input. t5g st timer5 gate input. ccp5 st cmos capture/compare/pwm5. rg5/mclr /v pp rg5 st general purpose input with wpu. mclr st master clear with internal pull-up. v pp hv programming voltage. av dd av dd power analog positive supply. av ss av ss power analog ground reference. v dd v dd power positive supply. v ss v ss power ground reference. table 1-2: pic16(l)f1526/7 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 12-1 ) register. 2: rc3, rc4, rd5 and rd6 read the i 2 c st input when i 2 c mode is enabled. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 15 pic16(l)f1526/7 2.0 enhanced mid-range cpu this family of devices contain an enhanced mid-range 8-bit cpu core. the cpu has 49 instructions. interrupt capability includes automatic context saving. the hardware stack is 16 levels deep and has overflow and underflow reset capability. direct, indirect, and relative addressing modes are available. two file select registers (fsrs) provide the ability to read program and data memory. automatic interrupt context saving 16-level stack with overflow and underflow file select registers instruction set figure 2-1: core block diagram data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 12 addr mux fsr reg status reg mux alu power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation clkin clkout v dd 8 8 brown-out reset 12 3 v ss internal oscillator block data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 addr mux fsr reg status reg mux alu w reg instruction decode & control timing generation v dd 8 8 3 v ss internal oscillator block 15 data bus 8 14 program bus instruction reg program counter 16-level stack (15-bit) direct addr 7 ram addr addr mux indirect addr fsr0 reg status reg mux alu instruction decode and control timing generation v dd 8 8 3 v ss internal oscillator block ram fsr reg fsr reg fsr1 reg 15 15 mux 15 program memory read (pmr) 12 fsr reg fsr reg bsr reg 5 configuration configuration configuration flash program memory downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 16 ? 2011-2015 microchip technology inc. 2.1 automatic interrupt context saving during interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. this saves stack space and user code. see section 7.5 ?automatic context saving? , for more information. 2.2 16-level stack with overflow and underflow these devices have an external stack memory 15 bits wide and 16 words deep. a stack overflow or under- flow will set the appropriate bit (stkovf or stkunf) in the pcon register, and if enabled will cause a soft- ware reset. see section 3.7 ?stack? for more details. 2.3 file select registers there are two 16-bit file select registers (fsr). fsrs can access all file registers and program memory, which allows one data pointer for all memory. when an fsr points to program memory, there is one additional instruction cycle in instructions using indf to allow the data to be fetched. general purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. there are also new instructions to support the fsrs. see section 3.8 ?indirect addressing? for more details. 2.4 instruction set there are 49 instructions for the enhanced mid-range cpu to support the features of the cpu. see section 24.0 ?instruction set summary? for more details. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 17 pic16(l)f1526/7 3.0 memory organization these devices contain the following types of memory: program memory - configuration words - device id -user id - flash program memory data memory - core registers - special function registers - general purpose ram - common ram the following features are associated with access and control of program memory and data memory: pcl and pclath stack indirect addressing 3.1 program memory organization the enhanced mid-range core has a 15-bit program counter capable of addressing a 32k x 14 program memory space. table 3-1 shows the memory sizes implemented for the pic16(l)f1526/7 family. accessing a location above these boundaries will cause a wrap-around within the implemented memory space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 3-1 and figure 3-2 ). 3.2 high endurance flash this device has a 128-byte section of high-endurance program flash memory (pfm) in lieu of data eeprom. this area is especially well suited for nonvolatile data storage that is expected to be updated frequently over the life of the end product. see section 11.2 ?flash program memory overview? for more information on writing data to pfm. refer to section section 3.2.1.2 ?indirect read with fsr? for more information about using the fsr registers to read byte data stored in pfm. table 3-1: device sizes and addresses device program memory space (words) last program memory address high-endurance flash memory address range (1) pic16f1526 pic16lf1526 8,192 1fffh 1f80h-1fffh pic16f1527 pic16lf1527 16,384 3fffh 3f80h-3fffh note 1: high-endurance flash applies to the low byte of each address in the range. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 18 ? 2011-2015 microchip technology inc. figure 3-1: program memory map and stack for pic16(l)f1526 figure 3-2: program memory map and stack for pic16(l)f1527 pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 3 page 2 page 3 17ffh 1800h 1fffh 2000h call, callw return, retlw interrupt , retfie pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 7 page 2 page 3 17ffh 1800h 1fffh 2000h page 4 page 7 3fffh 4000h call, callw return, retlw interrupt , retfie downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 19 pic16(l)f1526/7 3.2.1 reading program memory as data there are two methods of accessing constants in pro- gram memory. the first method is to use tables of retlw instructions. the second method is to set an fsr to point to the program memory. 3.2.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to create such a table is shown in example 3-1 . example 3-1: retlw instruction the brw instruction makes this type of table very sim- ple to implement. if your code must remain portable with previous generations of microcontrollers, then the brw instruction is not available so the older table read method must be used. 3.2.1.2 indirect read with fsr the program memory can be accessed as data by set- ting bit 7 of the fsrxh register and reading the match- ing indfx register. the moviw instruction will place the lower 8 bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the pro- gram memory via the fsr require one extra instruction cycle to complete. example 3-2 demonstrates access- ing the program memory via an fsr. the high directive will set bit<7> if a label points to a location in program memory. example 3-2: accessing program memory via fsr constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ; lots of code movlw data_index call constants ; the constant is in w constants dw data0 ;first constant dw data1 ;second constant dw data2 dw data3 my_function ; lots of code movlw data_index addlw low constants movwf fsr1l movlw high constants ;msb is set automatically movwf fsr1h btfsc status,c ;carry from addlw? incf fsr1h,f ;yes moviw 0[fsr1] ;the program memory is in w downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 20 ? 2011-2015 microchip technology inc. 3.3 data memory organization the data memory is partitioned in 32 memory banks with 128 bytes in a bank. each bank consists of ( figure 3-3 ): 12 core registers 20 special function registers (sfr) up to 80 bytes of general purpose ram (gpr) 16 bytes of common ram the active bank is selected by writing the bank number into the bank select register (bsr). unimplemented memory will read as 0 . all data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two file select registers (fsr). see section 3.8 ?indirect addressing? for more information. data memory uses a 12-bit address. the upper seven bits of the address define the bank address and the lower five bits select the registers/ram in that bank. 3.3.1 core registers the core registers contain the registers that directly affect the basic operation. the core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0bh/x8bh). these registers are listed below in ta b l e 3 - 2 . for detailed information, see tab l e 3 - 4 . table 3-2: core registers addresses bankx x00h or x80h indf0 x01h or x81h indf1 x02h or x82h pcl x03h or x83h status x04h or x84h fsr0l x05h or x85h fsr0h x06h or x86h fsr1l x07h or x87h fsr1h x08h or x88h bsr x09h or x89h wreg x0ah or x8ah pclath x0bh or x8bh intcon downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 21 pic16(l)f1526/7 3.3.1.1 status register the status register, shown in register 3-1 , contains: the arithmetic status of the alu the reset status the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 24.0 ?instruction set summary? ). 3.4 register definitions: status note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 3-1: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u to pd zd c (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as 0 bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 22 ? 2011-2015 microchip technology inc. 3.5 special function register the special function registers are registers used by the application to control the desired operation of peripheral functions in the device. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). the registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.5.1 general purpose ram there are up to 80 bytes of gpr in each data memory bank. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). 3.5.1.1 linear access to gpr the general purpose ram can be accessed in a non-banked method via the fsrs. this can simplify access to large memory structures. see section 3.8.2 ?linear data memory? for more information. 3.5.2 common ram there are 16 bytes of common ram accessible from all banks. figure 3-3: banked memory partitioning 3.5.3 device memory maps the memory maps for pic16(l)f1526/7 are shown in table 3-3 . 0bh 0ch 1fh 20h 6fh 70h 7fh 00h common ram (16 bytes) general purpose ram (80 bytes maximum) core registers (12 bytes) special function registers (20 bytes maximum) memory region 7-bit bank offset downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 23 pic16(l)f1526/7 table 3-3: pic16(l)f1526/7 memory map legend: = unimplemented data memory locations, read as 0 . note 1: pic16f1526/7 only. bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch 28ch portf 30ch trisf 38ch latf 00dh portb 08dh trisb 10dh latb 18dh anselb 20dh wpub 28dh portg 30dh trisg 38dh latg 00eh portc 08eh trisc 10eh latc 18eh 2 0 e h 2 8 e h 3 0 e h 3 8 e h 00fh portd 08fh trisd 10fh latd 18fh anseld 20fh wpud 28fh 3 0 f h 3 8 f h 010h porte 090h trise 110h late 190h ansele 210h wpue 290h 310h 390h 011h pir1 091h pie1 111h 191h pmadrl 211h ssp1buf 291h ccpr1l 311h ccpr3l 391h 012h pir2 092h pie2 112h 192h pmadrh 212h ssp1add 292h ccpr1h 312h ccpr3h 392h 013h pir3 093h pie3 113h 193h pmdatl 213h ssp1msk 293h ccp1con 313h ccp3con 393h 014h pir4 094h pie4 114h 194h pmdath 214h ssp1stat 294h 314h 394h iocbp 015h tmr0 095h option_reg 115h 195h pmcon1 215h ssp1con1 295h 315h 395h iocbn 016h tmr1l 096h pcon 116h borcon 196h pmcon2 216h ssp1con2 296h 316h 396h iocbf 017h tmr1h 097h wdtcon 117h fvrcon 197h vregcon (1) 217h ssp1con3 297h 317h 397h 018h t1con 098h 1 1 8 h 1 9 8 h 2 1 8 h 298h ccpr2l 318h ccpr4l 398h 019h t1gcon 099h osccon 119h 199h rc1reg 219h ssp2buf 299h ccpr2h 319h ccpr4h 399h 01ah tmr2 09ah oscstat 11ah 19ah tx1reg 21ah ssp2add 29ah ccp2con 31ah ccp4con 39ah 01bh pr2 09bh adresl 11bh 19bh sp1brg 21bh ssp2msk 29bh 3 1 b h 3 9 b h 01ch t2con 09ch adresh 11ch 19ch sp1brgh 21ch ssp2stat 29ch 31ch ccpr5l 39ch 01dh 09dh adcon0 11dh apfcon 19dh rc1sta 21dh ssp2con1 29dh ccptmrs0 31dh ccpr5 h 39dh 01eh 09eh adcon1 11eh 19eh tx1sta 21eh ssp2con2 29eh ccptmrs1 31eh ccp5con 39eh 01fh 0 9 f h 1 1 f h 19fh baud1con 21fh ssp2con3 29fh ccptmrs2 31fh 3 9 f h 020h general purpose register 80 bytes 0a0h general purpose register 80 bytes 120h general purpose register 80 bytes 1a0h general purpose register 80 bytes 220h general purpose register 80 bytes 2a0h general purpose register 80 bytes 320h general purpose register 80 bytes 3a0h general purpose register 80 bytes 06fh 0efh 16fh 1efh 26fh 2efh 36fh 3efh 070h common ram 0f0h common ram (accesses 70h C 7fh) 170h common ram (accesses 70h C 7fh) 1f0h common ram (accesses 70h C 7fh) 270h common ram (accesses 70h C 7fh) 2f0h common ram (accesses 70h C 7fh) 370h common ram (accesses 70h C 7fh) 3f0h common ram (accesses 70h C 7fh) 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 24 ? 2011-2015 microchip technology inc. table 3-3: pic16(l)f1526/7 memory map (continued) legend: = unimplemented data memory locations, read as 0 . note 1: pic16(l)f1527 only. bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 400h 40bh core registers ( ta b l e 3 - 2 ) 480h 48bh core registers ( ta b l e 3 - 2 ) 500h 50bh core registers ( ta b l e 3 - 2 ) 580h 58bh core registers ( ta b l e 3 - 2 ) 600h 60bh core registers ( ta b l e 3 - 2 ) 680h 68bh core registers ( ta b l e 3 - 2 ) 700h 70bh core registers ( ta b l e 3 - 2 ) 780h 78bh core registers ( ta b l e 3 - 2 ) 40ch anself 48ch 50ch unimplemented read as 0 58ch 60ch 68ch unimplemented read as 0 70ch unimplemented read as 0 78ch unimplemented read as 0 40dh anselg 48dh wpug 58dh 60dh 40eh 48eh 58eh 60eh 40fh 48fh 58fh 60fh 410h 490h 590h 610h 411h tmr3l 491h rc2reg 591h 611h ccpr6l 412h tmr3h 492h tx2reg 592h 612h ccpr6h 413h t3con 493h sp2brg 593h 613h ccp6con 414h t3gcon 494h sp2brgh 594h 614h ccpr7l 415h tmr4 495h rc2sta 595h tmr8 615h ccpr7h 416h pr4 496h tx2sta 596h pr8 616h ccp7con 417h t4con 497h baud2con 597h t8con 617h ccpr8l 418h tmr5l 498h 598h 618h ccpr8h 419h tmr5h 499h 599h 619h ccp8con 41ah t5con 49ah 59ah 61ah ccpr9l 41bh t5gcon 49bh 59bh 61bh ccpr9h 41ch tmr6 49ch 59ch tmr10 61ch ccp9con 41dh pr6 49dh 59dh pr10 61dh ccpr10l 41eh t6con 49eh 59eh t10con 61eh ccpr10h 41fh 49fh 51fh 59fh 61fh ccp10con 69fh 71fh 79fh 420h general purpose register 80 bytes 4a0h general purpose register 32 bytes 520h general purpose register 80 bytes (1) 5a0h general purpose register 80 bytes (1) 620h general purpose register 80 bytes (1) 6a0h general purpose register 80 bytes (1) 720h general purpose register 80 bytes (1) 7a0h general purpose register 80 bytes (1) 4bfh 4c0h general purpose register 48 bytes (1) 46fh 4efh 56fh 5efh 66fh 6efh 76fh 7efh 470h common ram (accesses 70h C 7fh) 4f0h common ram (accesses 70h C 7fh) 570h common ram (accesses 70h C 7fh) 5f0h common ram (accesses 70h C 7fh) 670h common ram (accesses 70h C 7fh) 6f0h common ram (accesses 70h C 7fh) 770h common ram (accesses 70h C 7fh) 7f0h common ram (accesses 70h C 7fh) 47fh 4ffh 57fh 5ffh 67fh 6ffh 77fh 7ffh downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 25 pic16(l)f1526/7 table 3-3: pic16(l)f1526/7 memory map (continued) legend: = unimplemented data memory locations, read as 0 . note 1: pic16(l)f1527 only. bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 800h 80bh core registers ( ta b l e 3 - 2 ) 880h 88bh core registers ( ta b l e 3 - 2 ) 900h 90bh core registers ( table 3-2 ) 980h 98bh core registers ( table 3-2 ) a00h a0bh core registers ( table 3-2 ) a80h a8bh core registers ( table 3-2 ) b00h b0bh core registers ( table 3-2 ) b80h b8bh core registers ( table 3-2 ) 80ch unimplemented read as 0 88ch unimplemented read as 0 90ch unimplemented read as 0 98ch unimplemented read as 0 a0ch unimplemented read as 0 a8ch unimplemented read as 0 b0ch unimplemented read as 0 b8ch unimplemented read as 0 81fh 89fh 91fh 820h general purpose register 80 bytes (1) 8a0h general purpose register 80 bytes (1) 920h general purpose register 80 bytes (1) 86fh 8efh 96fh 9efh a6fh aefh b6fh befh 870h common ram (accesses 70h C 7fh) 8f0h common ram (accesses 70h C 7fh) 970h common ram (accesses 70h C 7fh) 9f0h common ram (accesses 70h C 7fh) a70h common ram (accesses 70h C 7fh) af0h common ram (accesses 70h C 7fh) b70h common ram (accesses 70h C 7fh) bf0h common ram (accesses 70h C 7fh) 87fh 8ffh 97fh 9ffh a7fh affh b7fh bffh bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 c00h c0bh core registers ( ta b l e 3 - 2 ) c80h c8bh core registers ( ta b l e 3 - 2 ) d00h d0bh core registers ( table 3-2 ) d80h d8bh core registers ( table 3-2 ) e00h e0bh core registers ( table 3-2 ) e80h e8bh core registers ( table 3-2 ) f00h f0bh core registers ( table 3-2 ) c0ch c6fh unimplemented read as 0 c8ch cefh unimplemented read as 0 d0ch d6fh unimplemented read as 0 d8ch defh unimplemented read as 0 e0ch e6fh unimplemented read as 0 e8ch eefh unimplemented read as 0 f0ch f6fh unimplemented read as 0 c70h common ram (accesses 70h C 7fh) cf0h common ram (accesses 70h C 7fh) d70h common ram (accesses 70h C 7fh) df0h common ram (accesses 70h C 7fh) e70h common ram (accesses 70h C 7fh) ef0h common ram (accesses 70h C 7fh) f70h common ram (accesses 70h C 7fh) c7fh cffh d7fh dffh e7fh effh f7fh downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 26 ? 2011-2015 microchip technology inc. table 3-3: pic16(l)f1526 memory map (continued) legend: = unimplemented data memory locations, read as 0 . bank 31 f80h f8bh core registers ( ta b l e 3 - 2 ) f8ch fe3h unimplemented read as 0 fe4h status_shad fe5h wreg_shad fe6h bsr_shad fe7h pclath_shad fe8h fsr0l_shad fe9h fsr0h_shad feah fsr1l_shad febh fsr1h_shad fech fedh stkptr feeh tosl fefh tosh ff0h common ram (accesses 70h C 7fh) fffh downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 27 pic16(l)f1526/7 3.5.4 core function registers summary the core function registers listed in ta bl e 3 - 4 can be addressed from any bank. table 3-4: core function registers summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0-31 x00h or x80h indf0 addressing this location uses contents of fsr0h/fsr0l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or x81h indf1 addressing this location uses contents of fsr1h/fsr1l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or x82h pcl program counter (pc) least significant byte 0000 0000 0000 0000 x03h or x83h status t o pd zd cc ---1 1000 ---q quuu x04h or x84h fsr0l indirect data memory address 0 low pointer 0000 0000 uuuu uuuu x05h or x85h fsr0h indirect data memory address 0 high pointer 0000 0000 0000 0000 x06h or x86h fsr1l indirect data memory address 1 low pointer 0000 0000 uuuu uuuu x07h or x87h fsr1h indirect data memory address 1 high pointer 0000 0000 0000 0000 x08h or x88h bsr bsr4 bsr3 bsr2 bsr1 bsr0 ---0 0000 ---0 0000 x09h or x89h wreg working register 0000 0000 uuuu uuuu x0ah or x8ah pclath write buffer for the upper 7 bits of the program counter -000 0000 -000 0000 x0bh or x8bh intcon gie peie tmr0ie inte iocie tmr0if intf iocif 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 28 ? 2011-2015 microchip technology inc. table 3-2: special function register summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0 00ch porta porta data latch when written: porta pins when read xxxx xxxx uuuu uuuu 00dh portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 00eh portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 00fh portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 010h porte porte data latch when written: porte pins when read xxxx xxxx uuuu uuuu 011h pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 0000 0000 0000 0000 012h pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 000- 0000 000- 0000 013h pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 0000 0000 0000 0000 014h pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 0000 0000 0000 0000 015h tmr0 timer0 module register xxxx xxxx uuuu uuuu 016h tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 017h tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 018h t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync t m r 1 o n 0000 00-0 uuuu uu-u 019h t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 0000 0x00 uuuu uxuu 01ah tmr2 timer 2 module register 0000 0000 0000 0000 01bh pr2 timer 2 period register 1111 1111 1111 1111 01ch t2con t2outps<3:0> tmr2on t2ckps<1:0> -000 0000 -000 0000 01dh unimplemented 01eh unimplemented 01fh unimplemented bank 1 08ch trisa porta data direction register 1111 1111 1111 1111 08dh trisb portb data direction register 1111 1111 1111 1111 08eh trisc portc data direction register 1111 1111 1111 1111 08fh trisd portd data direction register 1111 1111 1111 1111 090h trise porte data direction register 1111 1111 1111 1111 091h pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 092h pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 000- 0000 000- 0000 093h pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 0000 0000 0000 0000 094h pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 0000 0000 0000 0000 095h option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 1111 1111 1111 1111 096h pcon stkovf stkunf r w d t rmclr ri por bor 00-1 11qq qq-q qquu 097h wdtcon w d t p s < 4 : 0 >s w d t e n --01 0110 --01 0110 098h unimplemented 099h osccon ircf<3:0> s c s < 1 : 0 > -011 1-00 -011 1-00 09ah oscstat soscr osts hfiofr lfiofr hfiofs 0-q0 --00 q-qq --0q 09bh adresl adc result register low xxxx xxxx uuuu uuuu 09ch adresh adc result register high xxxx xxxx uuuu uuuu 09dh adcon0 chs<4:0> go/done adon -000 0000 -000 0000 09eh adcon1 adfm adcs<2:0> adpref<1:0> 0000 --00 0000 --00 09fh unimplemented legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . note 1: pic16f1526/7 only. 2: unimplemented, read as 1 . downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 29 pic16(l)f1526/7 bank 2 10ch lata porta data latch xxxx xxxx uuuu uuuu 10dh latb portb data latch xxxx xxxx uuuu uuuu 10eh latc portc data latch xxxx xxxx uuuu uuuu 10fh latd portd data latch xxxx xxxx uuuu uuuu 110h late porte data latch xxxx xxxx uuuu uuuu 111h to 115h unimplemented 116h borcon sboren borfs borrdy 10-- ---q uu-- ---u 117h fvrcon fvren fvrrdy tsen tsrng a d f v r < 1 : 0 > 0q00 0000 0q00 0000 118h to 11ch unimplemented 11dh apfcon t3ckisel ccp2sel ---- --00 ---- --00 11eh unimplemented 11fh unimplemented bank 3 18ch ansela ansa5 ansa3 ansa2 ansa1 ansa0 --1- 1111 --1- 1111 18dh anselb ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 --11 1111 --11 1111 18eh anselc unimplemented 18fh anseld ansd3 ansd2 ansd1 ansd0 ---- 1111 ---- 1111 190h ansele anse2 anse1 anse0 ---- -111 ---- -111 191h pmadrl program memory address register low byte 0000 0000 0000 0000 192h pmadrh (2) program memory address register high byte 1000 0000 1000 0000 193h pmdatl program memory data register low byte xxxx xxxx uuuu uuuu 194h pmdath program memory data register high byte --xx xxxx --uu uuuu 195h pmcon1 (2) cfgs lwlo free wrerr wren wr rd 1000 x000 1000 q000 196h pmcon2 program memory control register 2 0000 0000 0000 0000 197h vregcon (1) v r e g p m reserved ---- --01 ---- --01 198h unimplemented 199h rc1reg usart receive data register 0000 0000 0000 0000 19ah tx1reg usart transmit data register 0000 0000 0000 0000 19bh sp1brg brg<7:0> 0000 0000 0000 0000 19ch sp1brgh brg<15:8> 0000 0000 0000 0000 19dh rc1sta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19eh tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 19fh baud1con abdovf rcidl sckp brg16 wue abden 01-0 0-00 01-0 0-00 table 3-2: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . note 1: pic16f1526/7 only. 2: unimplemented, read as 1 . downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 30 ? 2011-2015 microchip technology inc. bank 4 20ch unimplemented 20dh wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 1111 1111 1111 1111 20eh unimplemented 20fh wpud wpud7 wpud6 wpud5 wpud4 wpud3 wpud2 wpud1 wpud0 1111 1111 1111 1111 210h wpue wpue7 wpue6 wpue5 wpue4 wpue3 wpue2 wpue1 wpue0 1111 1111 1111 1111 211h ssp1buf synchronous serial port receive buffer/transmit registe r xxxx xxxx uuuu uuuu 212h ssp1add synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 213h ssp1msk synchronous serial port (i 2 c mode) address mask register 1111 1111 1111 1111 214h ssp1stat smp cke d/a psr / w ua bf 0000 0000 0000 0000 215h ssp1con1 wcol sspov sspen ckp sspm<3:0> 0000 0000 0000 0000 216h ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 217h ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 218h unimplemented 219h ssp2buf synchronous serial port receive buffer/transmit registe r xxxx xxxx uuuu uuuu 21ah ssp2add synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 21bh ssp2msk synchronous serial port (i 2 c mode) address mask register 1111 1111 1111 1111 21ch ssp2stat smp cke d/a psr / w ua bf 0000 0000 0000 0000 21dh ssp2con1 wcol sspov sspen ckp sspm<3:0> 0000 0000 0000 0000 21eh ssp2con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 21fh ssp2con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 bank 5 28ch portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 xxxx xxxx uuuu uuuu 28dh portg rg5 rg4 rg3 rg2 rg1 rg0 --xx xxxx --uu uuuu 28eh unimplemented 28fh unimplemented 290h unimplemented 291h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 292h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 293h ccp1con dc1b<1:0> ccp1m<3:0> --00 0000 --00 0000 294h unimplemented 295h unimplemented 296h unimplemented 297h unimplemented 298h ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 299h ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 29ah ccp2con dc2b<1:0> ccp2m<3:0> --00 0000 --00 0000 29bh unimplemented 29ch unimplemented 29dh ccptmrs0 c4tsel<1:0> c3tsel<1:0> c2tsel<1:0> c1tsel<1:0> 0000 0000 0000 0000 29eh ccptmrs1 c8tsel<1:0> c7tsel<1:0> c6tsel<1:0> c5tsel<1:0> 0000 0000 0000 0000 29fh ccptmrs2 c10tsel<1:0> c9tsel<1:0> ---- 0000 ---- 0000 table 3-2: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . note 1: pic16f1526/7 only. 2: unimplemented, read as 1 . downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 31 pic16(l)f1526/7 bank 6 30ch trisf trisf7 trisf6 trisf5 tri sf4 trisf3 trisf2 trisf1 trisf0 1111 1111 1111 1111 30dh trisg (2) trisg4 trisg3 trisg2 trisg1 trisg0 --11 1111 --11 1111 30eh unimplemented 30fh unimplemented 310h unimplemented 311h ccpr3l capture/compare/pwm register 3 (lsb) xxxx xxxx uuuu uuuu 312h ccpr3h capture/compare/pwm register 3 (msb) xxxx xxxx uuuu uuuu 313h ccp3con dc3b<1:0> ccp3m<3:0> --00 0000 --00 0000 314h unimplemented 315h unimplemented 316h unimplemented 317h unimplemented 318h ccpr4l capture/compare/pwm register 4 (lsb) xxxx xxxx uuuu uuuu 319h ccpr4h capture/compare/pwm register 4 (msb) xxxx xxxx uuuu uuuu 31ah ccp4con dc4b<1:0> ccp4m<3:0> --00 0000 --00 0000 31bh unimplemented 31ch ccpr5l capture/compare/pwm register 5 (lsb) xxxx xxxx uuuu uuuu 31dh ccpr5h capture/compare/pwm register 5 (msb) xxxx xxxx uuuu uuuu 31eh ccp5con dc5b<1:0> ccp5m<3:0> --00 0000 --00 0000 31fh unimplemented bank 7 38ch latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx xxxx uuuu uuuu 38dh latg latg4 latg3 latg2 latg1 latg0 ---x xxxx ---u uuuu 38eh to 393h unimplemented 394h iocbp iocbp7 iocbp6 iocbp5 ioc bp4 iocbp3 iocbp2 iocbp1 iocbp0 0000 0000 0000 0000 395h iocbn iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 0000 0000 0000 0000 396h iocbf iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 0000 0000 0000 0000 397h to 39fh unimplemented table 3-2: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . note 1: pic16f1526/7 only. 2: unimplemented, read as 1 . downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 32 ? 2011-2015 microchip technology inc. bank 8 40ch anself ansf7 ansf6 ansf5 ansf4 ansf3 ansf2 ansf1 ansf0 1111 1111 1111 1111 40dh anselg ansg4 ansg3 ansg2 ansg1 ---1 111- ---1 111- 40eh unimplemented 40fh unimplemented 410h unimplemented 411h tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu 412h tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu 413h t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync t m r 3 o n 0000 00-0 uuuu uu-u 414h t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/ done t3gval t3gss<1:0> 0000 0x00 uuuu uxuu 415h tmr4 timer 4 module register 0000 0000 0000 0000 416h pr4 timer 4 period register 1111 1111 1111 1111 417h t4con t4outps<3:0> tmr4on t4ckps<1:0> -000 0000 -000 0000 418h tmr5l holding register for the least significant byte of the 16-bit tmr5 register xxxx xxxx uuuu uuuu 419h tmr5h holding register for the most significant byte of the 16-bit tmr5 register xxxx xxxx uuuu uuuu 41ah t5con tmr5cs<1:0> t5ckps<1:0> soscen t5sync t m r 5 o n 0000 00-0 uuuu uu-u 41bh t5gcon tmr5ge t5gpol t5gtm t5gspm t5ggo/ done t5gval t5gss<1:0> 0000 0x00 uuuu uxuu 41ch tmr6 timer 6 module register 0000 0000 0000 0000 41dh pr6 timer 6 period register 1111 1111 1111 1111 41eh t6con t6outps<3:0> tmr6on t6ckps<1:0> -000 0000 -000 0000 41fh unimplemented bank 9 48ch unimplemented 48dh wpug w p u g 5 --1- ---- --1- ---- 48dh to 490h unimplemented 491h rc2reg usart receive data register 0000 0000 0000 0000 492h tx2reg usart transmit data register 0000 0000 0000 0000 493h sp2brg brg<7:0> 0000 0000 0000 0000 494h sp2brgh brg<15:8> 0000 0000 0000 0000 495h rc2sta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 496h tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 497h baud2con abdovf rcidl sckp brg16 wue abden 01-0 0-00 01-0 0-00 498h to 49fh unimplemented table 3-2: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . note 1: pic16f1526/7 only. 2: unimplemented, read as 1 . downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 33 pic16(l)f1526/7 bank 10 50ch 51fh unimplemented bank 11 58ch 594h unimplemented 595h tmr8 timer 8 module register 0000 0000 0000 0000 596h pr8 timer 8 period register 1111 1111 1111 1111 597h t8con t8outps<3:0> tmr8on t8ckps<1:0> -000 0000 -000 0000 598h 59bh unimplemented 59ch tmr10 timer 10 module register 0000 0000 0000 0000 59dh pr10 timer 10 period register 1111 1111 1111 1111 59eh t10con t10outps<3:0> tmr10on t10ckps<1:0> -000 0000 -000 0000 59fh unimplemented bank 12 60ch 610h unimplemented 611h ccpr6l capture/compare/pwm register 6 (lsb) xxxx xxxx uuuu uuuu 612h ccpr6h capture/compare/pwm register 6 (msb) xxxx xxxx uuuu uuuu 613h ccp6con dc6b<1:0> ccp6m<3:0> --00 0000 --00 0000 614h ccpr7l capture/compare/pwm register 7 (lsb) xxxx xxxx uuuu uuuu 615h ccpr7h capture/compare/pwm register 7 (msb) xxxx xxxx uuuu uuuu 616h ccp7con dc7b<1:0> ccp7m<3:0> --00 0000 --00 0000 617h ccpr8l capture/compare/pwm register 8 (lsb) xxxx xxxx uuuu uuuu 618h ccpr8h capture/compare/pwm register 8 (msb) xxxx xxxx uuuu uuuu 619h ccp8con dc8b<1:0> ccp8m<3:0> --00 0000 --00 0000 61ah ccpr9l capture/compare/pwm register 9 (lsb) xxxx xxxx uuuu uuuu 61bh ccpr9h capture/compare/pwm register 9 (msb) xxxx xxxx uuuu uuuu 61ch ccp9con dc9b<1:0> ccp9m<3:0> --00 0000 --00 0000 61dh ccpr10l capture/compare/pwm register 10 (lsb) xxxx xxxx uuuu uuuu 61eh ccpr10h capture/compare/pwm register 10 (msb) xxxx xxxx uuuu uuuu 61fh ccp10con dc10b<1:0> ccp10m<3:0> --00 0000 --00 0000 bank 13-30 x0ch or x8ch to x1fh or x9fh unimplemented table 3-2: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . note 1: pic16f1526/7 only. 2: unimplemented, read as 1 . downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 34 ? 2011-2015 microchip technology inc. bank 31 f8ch fe3h unimplemented fe4h status_shad z_shad dc_shad c_shad ---- -xxx ---- -uuu fe5h wreg_shad working register normal (non-icd) shadow xxxx xxxx uuuu uuuu fe6h bsr_shad bank select register normal (non-icd) shadow ---x xxxx ---u uuuu fe7h pclath_shad program counter latch high register normal (non-icd) shadow -xxx xxxx uuuu uuuu fe8h fsr0l_shad indirect data memory address 0 low pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu fe9h fsr0h_shad indirect data memory address 0 high pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu feah fsr1l_shad indirect data memory address 1 low pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu febh fsr1h_shad indirect data memory address 1 high pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu fech unimplemented fedh stkptr current stack pointer ---1 1111 ---1 1111 feeh tosl top of stack low byte xxxx xxxx uuuu uuuu fefh tosh top of stack high byte -xxx xxxx -uuu uuuu table 3-2: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations are unimplemented, read as 0 . note 1: pic16f1526/7 only. 2: unimplemented, read as 1 . downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 35 pic16(l)f1526/7 3.6 pcl and pclath the program counter (pc) is 15 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<14:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-4 shows the five situations for the loading of the pc. figure 3-4: loading of pc in different situations 3.6.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<14:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writ- ing the desired upper 7 bits to the pclath register. when the lower 8 bits are written to the pcl register, all 15 bits of the program counter will change to the values contained in the pclath register and those being writ- ten to the pcl register. 3.6.2 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to application note an556, ?implementing a table read? (ds00556). 3.6.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. the callw instruction enables computed calls by com- bining pclath and w to form the destination address. a computed callw is accomplished by loading the w register with the desired address and executing callw . the pcl register is loaded with the value of w and pch is loaded with pclath. 3.6.4 branching the branching instructions add an offset to the pc. this allows relocatable code and code that crosses page boundaries. there are two forms of branching, brw and bra . the pc will have incremented to fetch the next instruction in both cases. when using either branching instruction, a pcl memory boundary may be crossed. if using brw , load the w register with the desired unsigned address and execute brw . the entire pc will be loaded with the address pc + 1 + w. if using bra , the entire pc will be loaded with pc + 1 +, the signed value of the operand of the bra instruction. pcl pch 0 14 pc 0 6 7 alu result 8 pclath pcl pch 0 14 pc 0 6 4 opcode <10:0> 11 pclath pcl pch 0 14 pc 0 6 7 w 8 pclath instruction with pcl as destination goto, call callw pcl pch 0 14 pc pc + w 15 brw pcl pch 0 14 pc pc + opcode <8:0> 15 bra downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 36 ? 2011-2015 microchip technology inc. 3.7 stack all devices have a 16-level x 15-bit wide hardware stack (refer to figures 3-5 through 3-8 ). the stack space is not part of either program or data space. the pc is pushed onto the stack when call or callw instructions are executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer if the stvren bit is programmed to 0 (configuration words). this means that after the stack has been pushed sixteen times, the seventeenth push overwrites the value that was stored from the first push. the eighteenth push overwrites the second push (and so on). the stkovf and stkunf flag bits will be set on an over- flow/underflow, regardless of whether the reset is enabled. 3.7.1 accessing the stack the stack is available through the tosh, tosl and stkptr registers. stkptr is the current value of the stack pointer. tosh:tosl register pair points to the top of the stack. both registers are read/writable. tos is split into tosh and tosl due to the 15-bit size of the pc. to access the stack, adjust the value of stkptr, which will position tosh:tosl, then read/write to tosh:tosl. stkptr is 5 bits to allow detection of overflow and underflow. during normal program operation, call, callw and interrupts will increment stkptr while retlw , return , and retfie will decrement stkptr. at any time stkptr can be inspected to see how much stack is left. the stkptr always points at the currently used place on the stack. therefore, a call or callw will increment the stkptr and then write the pc, and a return will unload the pc and then decrement the stkptr. reference figures 3-5 through 3-8 for examples of accessing the stack. figure 3-5: accessing the stack example 1 note 1: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, callw , return , retlw and retfie instructions or the vectoring to an interrupt address. note: care should be taken when modifying the stkptr while interrupts are enabled. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x0000 stkptr = 0x1f initial stack configuration: after reset, the stack is empty. the empty stack is initialized so the stack pointer is pointing at 0x1f. if the stack overflow/underflow reset is enabled, the tosh/tosl registers will return 0 . if the stack overflow/underflow reset is disabled, the tosh/tosl registers will return the contents of stack address 0x0f. 0x1f stkptr = 0x1f stack reset disabled (stvren = 0 ) stack reset enabled (stvren = 1 ) tosh:tosl tosh:tosl downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 37 pic16(l)f1526/7 figure 3-6: accessing the stack example 2 figure 3-7: accessing the stack example 3 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x00 this figure shows the stack configuration after the first call or a single interrupt. if a return instruction is executed, the return addre ss will be placed in the program counter and the stack pointer decremented to the empty state (0x1f). tosh:tosl 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 return address 0x06 return address 0x05 return address 0x04 return address 0x03 return address 0x02 return address 0x01 return address 0x00 stkptr = 0x06 after seven call s or six call s and an interrupt, the stack looks like the figure on the left. a series of return instructions will repeatedly place the return addresses into the program counter and pop the stack. tosh:tosl downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 38 ? 2011-2015 microchip technology inc. figure 3-8: accessing the stack example 4 3.7.2 overflow/underflow reset if the stvren bit in configuration words is programmed to 1 , the device will be reset if the stack is pushed beyond the sixteenth level or poped beyond the first level, setting the appropriate bits (stkovf or stkunf, respectively) in the pcon register. 3.8 indirect addressing the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the file select registers (fsr). if the fsrn address specifies one of the two indfn registers, the read will return 0 and the write will not occur (though status bits may be affected). the fsrn register value is created by the pair fsrnh and fsrnl. the fsr registers form a 16-bit address that allows an addressing space with 65536 locations. these locations are divided into three memory regions: traditional data memory linear data memory program flash memory 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x10 when the stack is full, the next call or an interrupt will set the stack pointer to 0x10. this is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. if the stack overflow/underflow reset is enabled, a reset will occur and location 0x00 will not be overwritten. return address return address return address return address return address return address return address return address return address return address return address return address return address return address return address tosh:tosl downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 39 pic16(l)f1526/7 figure 3-9: indirect addressing 0x0000 0x0fff traditional fsr address range data memory 0x1000 reserved linear data memory reserved 0x2000 0x29af 0x29b0 0x7fff 0x8000 0xffff 0x0000 0x0fff 0x0000 0x7fff program flash memory note: not all memory regions are completely implemented. consult device memory tables for memory limit s. 0x1fff downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 40 ? 2011-2015 microchip technology inc. 3.8.1 traditional data memory the traditional data memory is a region from fsr address 0x000 to fsr address 0xfff. the addresses correspond to the absolute addresses of all sfr, gpr and common registers. figure 3-10: traditio nal data memory map indirect addressing direct addressing bank select location select 4b s r 6 0 from opcode fsrxl 70 bank select location select 00000 00001 00010 11111 0x00 0x7f bank 0 bank 1 bank 2 bank 31 0 fsrxh 70 0000 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 41 pic16(l)f1526/7 3.8.2 linear data memory the linear data memory is the region from fsr address 0x2000 to fsr address 0x29af. this region is a virtual region that points back to the 80-byte blocks of gpr memory in all the banks. unimplemented memory reads as 0x00. use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the fsr beyond one bank will go directly to the gpr memory of the next bank. the 16 bytes of common memory are not included in the linear data memory region. figure 3-11: linear data memory map 3.8.3 program flash memory to make constant data access easier, the entire program flash memory is mapped to the upper half of the fsr address space. when the msb of fsrnh is set, the lower 15 bits are the address in program memory which will be accessed through indf. only the lower 8 bits of each memory location is accessible via indf. writing to the program flash memory cannot be accomplished via the fsr/indf interface. all instructions that access program flash memory via the fsr/indf interface will require one additional instruction cycle to complete. figure 3-12: program flash memory map 7 0 1 7 0 0 location select 0x2000 fsrnh fsrnl 0x020 bank 0 0x06f 0x0a0 bank 1 0x0ef 0x120 bank 2 0x16f 0xf20 bank 30 0xf6f 0x29af 0 7 1 7 0 0 location select 0x8000 fsrnh fsrnl 0x0000 0x7fff 0xffff program flash memory (low 8 bits) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 42 ? 2011-2015 microchip technology inc. 4.0 device configuration device configuration consists of configuration words, code protection and device id. 4.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 at 8007h and configuration word 2 at 8008h. note: the debug bit in configuration word 2 is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a ' 1 '. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 43 pic16(l)f1526/7 4.2 register definitions: configuration words register 4-1: config1: configuration word 1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 fcmen ieso clkouten boren<1:0> bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp mclre pwrte wdte<1:0> fosc<2:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as 1 0 = bit is cleared 1 = bit is set -n = value when blank or after bulk erase bit 13 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled bit 12 ieso: internal external switchover bit 1 = internal/external switchover mode is enabled 0 = internal/external switchover mode is disabled bit 11 clkouten : clock out enable bit if fosc configuration bits are set to lp, xt, hs modes : this bit is ignored, clkout function is disabled. oscillator function on the clkout pin. all other fosc modes : 1 = clkout function is disabled. i/o function on the clkout pin. 0 = clkout function is enabled on the clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit of the borcon register 00 = bor disabled bit 8 unimplemented: read as 1 bit 7 cp : code protection bit 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 : this bit is ignored. if lvp bit = 0 : 1 =mclr /v pp pin function is mclr ; weak pull-up enabled. 0 =mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpug5 bit. bit 5 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 4-3 wdte<1:0>: watchdog timer enable bit 11 = wdt enabled 10 = wdt enabled while running and disabled in sleep 01 = wdt controlled by the swdten bit in the wdtcon register 00 = wdt disabled downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 44 ? 2011-2015 microchip technology inc. bit 2-0 fosc<2:0>: oscillator selection bits 111 = ech: external clock, high-power mode (4-20 mhz): device clock supplied to clkin pin 110 = ecm: external clock, medium-power mode (0.5-4 mhz): device clock supplied to clkin pin 101 = ecl: external clock, low-power mode (0-0.5 mhz): device clock supplied to clkin pin 100 = intosc oscillator: i/o function on clkin pin 011 = extrc oscillator: external rc circuit connected to clkin pin 010 = hs oscillator: high-speed crystal/resonator connected between osc1 and osc2 pins 001 = xt oscillator: crystal/resonator connected between osc1 and osc2 pins 000 = lp oscillator: low-power crystal connected between osc1 and osc2 pins register 4-1: conf ig1: config uration word 1 (continued) downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 45 pic16(l)f1526/7 register 4-2: config2: configuration word 2 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 lvp debug lpbor borv stvren bit 13 bit 8 u-1 u-1 u-1 r/p-1 u-1 u-1 r/p-1 r/p-1 vcapen (1) w r t < 1 : 0 > bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as 1 0 = bit is cleared 1 = bit is set -n = value when blank or after bulk erase bit 13 lvp: low-voltage programming enable bit 1 = low-voltage programming enabled 0 = high-voltage on mclr must be used for programming bit 12 debug : in-circuit debugger mode bit 1 = in-circuit debugger disabled, icspclk and icspdat are general purpose i/o pins 0 = in-circuit debugger enabled, icspclk and icspdat are dedicated to the debugger bit 11 l pbor : low-power bor bit 1 = low-power bor is disabled 0 = low-power bor is enabled bit 10 borv: brown-out reset voltage selection bit (2) 1 = brown-out reset voltage ( vbor ), low trip point selected. 0 = brown-out reset voltage ( vbor ), high trip point selected. bit 9 stvren: stack overflow/underflow reset enable bit 1 = stack overflow or underflow will cause a reset 0 = stack overflow or underflow will not cause a reset bit 8-5 unimplemented: read as 1 bit 4 vcapen : voltage regulator capacitor enable bits (1) if pic16lf1526/7 ( regulator disabled) : these bits are ignored. all v cap pin functions are disabled. if pic16f1526/7 ( regulator enabled) : 0 =v cap functionality is enabled on rf0. 1 =all v cap pin functions are disabled bit 3-2 unimplemented: read as 1 bit 1-0 wrt<1:0>: flash memory self-write protection bits 8 kw flash memory ( pic16(l)f1526 o nly) : 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to 1fffh may be modified by pmcon control 01 = 000h to fffh write-protected, 1000h to 1fffh may be modified by pmcon control 00 = 000h to 1fffh write-protected, no addresses may be modified by pmcon control 16 kw flash memory ( pic16(l)f1527 o nly) : 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to 3fffh may be modified by pmcon control 01 = 000h to 1fffh write-protected, 2000h to 3fffh may be modified by pmcon control 00 = 000h to 3fffh write-protected, no addresses may be modified by pmcon control note 1: pic16f1526/7 only. 2: see vbor parameter for specific trip point voltages. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 46 ? 2011-2015 microchip technology inc. 4.3 code protection code protection allows the device to be protected from unauthorized access. program memory protection is controlled independently. internal access to the program memory is unaffected by any code protection setting. 4.3.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in configuration words. when cp = 0 , external reads and writes of program memory are inhibited and a read will return all 0 s. the cpu can continue to read program memory, regardless of the protection bit settings. writing the program memory is dependent upon the write protection setting. see section 4.4 ?write protection? for more information. 4.4 write protection write protection allows the device to be protected from unintended self-writes. applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in configuration words define the size of the program memory block that is protected. 4.5 user id four memory locations (8000h-8003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are readable and writable during normal execution. see section 11.5 ?user id, device id and configuration word access? for more information on accessing these memory locations. for more information on checksum calculation, see the pic16f/lf151x/152x memory programming specification (ds41422). downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 47 pic16(l)f1526/7 4.6 device id and revision id the memory location 8006h is where the device id and revision id are stored. the upper nine bits hold the device id. the lower five bits hold the revision id. see section 11.5 ?user id, device id and configuration word access? for more information on accessing these memory locations. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. register 4-3: devid: device id register rrrrrr dev<8:3> bit 13 bit 8 rrrrrrrr dev<2:0> rev<4:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as 1 1 = bit is set 0 = bit is cleared -n/n = value at por and bor/value at all other resets bit 13-5 dev<8:0>: device id bits bit 4-0 rev<4:0>: revision id bits these bits are used to identify the revision (see table under dev<8:0> above). device devid<13:0> values dev<8:0> rev<4:0> pic16f1526 01 0101 100 x xxxx pic16f1527 01 0101 101 x xxxx pic16lf1526 01 0101 110 x xxxx pic16lf1527 01 0101 111 x xxxx downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 48 ? 2011-2015 microchip technology inc. 5.0 oscillator module (with fail-safe clock monitor) 5.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 5-1 illustrates a block diagram of the oscillator module. clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. additional clock features include: selectable system clock source between external or internal sources via software. two-speed start-up mode, which minimizes latency between external oscillator start-up and code execution. fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ec or rc modes) and switch automatically to the internal oscillator. oscillator start-up timer (ost) ensures stability of crystal oscillator sources fast start-up oscillator allows internal circuits to power up and stabilize before switching to the 16 mhz hfintosc the oscillator module can be configured in one of eight clock modes. 1. ecl C external clock low-power mode (0 mhz to 0.5 mhz) 2. ecm C external clock medium-power mode (0.5 mhz to 4 mhz) 3. ech C external clock high-power mode (4 mhz to 20 mhz) 4. lp C 32 khz low-power crystal mode. 5. xt C medium gain crystal or ceramic resonator oscillator mode (up to 4 mhz) 6. hs C high gain crystal or ceramic resonator mode (4 mhz to 20 mhz) 7. rc C external resistor-capacitor (rc). 8. intosc C internal oscillator (31 khz to 16 mhz). clock source modes are selected by the fosc<2:0> bits in the configuration words. the fosc bits determine the type of oscillator that will be used when the device is first powered. the ec clock mode relies on an external logic level signal as the device clock source. the lp, xt and hs clock modes require an external crystal or resonator to be connected to the device. each mode is optimized for a different frequency range. the rc clock mode requires an external resistor and capacitor to set the oscillator frequency. the intosc internal oscillator block produces a low and high-frequency clock source, designated lfintosc and hfintosc. (see internal oscillator block, figure 5-1 ). a wide selection of device clock frequencies may be derived from these two clock sources. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 49 pic16(l)f1526/7 figure 5-1: simplified pic ? mcu clock source block diagram osc2 osc1 primary oscillator (osc) sosco/ t1cki sosci secondary oscillator (sosc) 16 mhz primary osc start-up osc lf-intosc (31.25 khz) intosc divide circuit ircf<3:0> intosc primary clock secondary clock clock switch mux 01 001x low power mode event switch (scs<1:0>) 2 4 secondary oscillator primary oscillator internal oscillator hf-16 mhz hf-4 mhz hf-2 mhz hf-1 mhz hf-500 khz hf-250 khz hf-125 khz hf-62.5 khz hf-31.25 khz lf-31 khz hf-8 mhz internal oscillator mux 4 1111 1110 1101 1100 1011 1010/ 0111 1001/ 0110 1000/ 0101 0100 0011 0010 0001 0000 /1/2 /4 /8 /16 /32 /64 /128 /256 /512 start-up control logic downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 50 ? 2011-2015 microchip technology inc. 5.2 clock source types clock sources can be classified as external or internal. external clock sources rely on external circuitry for the clock source to function. examples are: oscillator modules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt and hs modes) and resistor-capacitor (rc) mode circuits. internal clock sources are contained within the oscillator module. the internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 mhz high-frequency internal oscillator and the 31 khz low-frequency internal oscillator (lfintosc). the system clock can be selected between external or internal clock sources via the system clock select (scs) bits in the osccon register. see section 5.3 ?clock switching? for additional information. 5.2.1 external clock sources an external clock source can be used as the device system clock by performing one of the following actions: program the fosc<2:0> bits in the configuration words to select an external clock source that will be used as the default system clock upon a device reset. write the scs<1:0> bits in the osccon register to switch the system clock source to: - secondary oscillator during run-time, or - an external clock source determined by the value of the fosc bits. see section 5.3 ?clock switching? for more informa- tion. 5.2.1.1 ec mode the external clock (ec) mode allows an externally generated logic level signal to be the system clock source. when operating in this mode, an external clock source is connected to the osc1 input. osc2/clkout is available for general purpose i/o or clkout. figure 5-2 shows the pin connections for ec mode. ec mode has three power modes to select from through configuration words: high power, 4-20 mhz (fosc = 111 ) medium power, 0.5-4 mhz (fosc = 110 ) low power, 0-0.5 mhz (fosc = 101 ) the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 5-2: external clock (ec) mode operation 5.2.1.2 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 ( figure 5-3 ). the three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is designed to drive only 32.768 khz tuning-fork type crystals (watch crystals). xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current consumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting. figure 5-3 and figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. osc1/clkin osc2/clkout clock from ext. system pic ? mcu f osc /4 or i/o (1) note 1: output depends upon clkouten bit of the configuration words. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 51 pic16(l)f1526/7 figure 5-3: quartz crystal operation (lp, xt or hs mode) figure 5-4: ceramic resonator operation (xt or hs mode) 5.2.1.3 oscillator start-up timer (ost) if the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations from osc1. this occurs following a power-on reset (por) and when the power-up timer (pwrt) has expired (if configured), or a wake-up from sleep. during this time, the program counter does not increment and program execution is suspended, unless either fscm or two-speed start-up are enabled. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. in order to minimize latency between external oscillator start-up and code execution, the two-speed clock start-up mode can be selected (see section 5.4 ?two-speed clock start-up mode? ). note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: an826, crystal oscillator basics and crystal selection for rfpic ? and pic ? devices (ds00826) an849, basic pic ? oscillator design (ds00849) an943, practical pic ? oscillator analysis and design (ds00943) an949, making your oscillator work (ds00949) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clkout note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clkout downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 52 ? 2011-2015 microchip technology inc. 5.2.1.4 secondary oscillator the secondary oscillator is a separate crystal oscillator that is associated with the timer1 peripheral. it is opti- mized for timekeeping operations with a 32.768 khz crystal connected between the sosco and sosci device pins. the secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. refer to section 5.3 ?clock switching? for more information. figure 5-5: quartz crystal operation (secondary oscillator) 5.2.1.5 external rc mode the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. the rc circuit connects to osc1. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined the clkouten bit in configuration words. figure 5-6 shows the external rc mode connections. figure 5-6: external rc modes the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. other factors affecting the oscillator frequency are: threshold voltage variation component tolerances packaging variations in capacitance the user also needs to take into account variation due to tolerance of the external rc components used. note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: an826, crystal oscillator basics and crystal selection for rfpic ? and pic ? devices (ds00826) an849, basic pic ? oscillator design (ds00849) an943, practical pic ? oscillator analysis and design (ds00943) an949, making your oscillator work (ds00949) tb097, interfacing a micro crystal ms1v-t1k 32.768 khz tuning fork crystal to a pic16f690/ss (ds91097) an1288, design practices for low-power external oscillators (ds01288) c1 c2 32.768 khz sosci to internal logic pic ? mcu crystal sosco quartz osc2/clkout c ext r ext pic ? mcu osc1/clkin f osc /4 or internal clock v dd v ss recommended values: 10 k ? ? r ext ? 100 k ? , <3v 3 k ? ? r ext ? 100 k ? , 3-5v c ext > 20 pf, 2-5v note 1: output depends upon clkouten bit of the configuration words. i/o (1) downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 53 pic16(l)f1526/7 5.2.2 internal clock sources the device may be configured to use the internal oscil- lator block as the system clock by performing one of the following actions: program the fosc<2:0> bits in configuration words to select the intosc clock source, which will be used as the default system clock upon a device reset. write the scs<1:0> bits in the osccon register to switch the system clock source to the internal oscillator during run-time. see section 5.3 ?clock switching? for more information. in intosc mode, osc1/clkin is available for general purpose i/o. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined by the clkouten bit in configuration words. the internal oscillator block has two independent oscillators that provides the internal system clock source. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 16 mhz. 2. the lfintosc (low-frequency internal oscillator) is uncalibrated and operates at 31 khz. 5.2.2.1 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 16 mhz internal clock source. the output of the hfintosc connects to a postscaler and multiplexer (see figure 5-1 ). the frequency derived from the hfintosc can be selected via software using the ircf<3:0> bits of the osccon register. see section 5.2.2.4 ?internal oscillator clock switch timing? for more information. the hfintosc is enabled by: configure the ircf<3:0> bits of the osccon register for the desired hf frequency, and fosc<2:0> = 100 , or set the system clock source (scs) bits of the osccon register to 1x . a fast start-up oscillator allows internal circuits to power-up and stabilize before switching to hfintosc. the high-frequency internal oscillator ready bit (hfiofr) of the oscstat register indicates when the hfintosc is running. the high-frequency internal oscillator stable bit (hfiofs) of the oscstat register indicates when the hfintosc is running within 0.5% of its final value. 5.2.2.2 lfintosc the low-frequency internal oscillator (lfintosc) is an uncalibrated 31 khz internal clock source. the output of the lfintosc connects to a multiplexer (see figure 5-1 ). select 31 khz, via software, using the ircf<3:0> bits of the osccon register. see section 5.2.2.4 ?internal oscillator clock switch timing? for more information. the lfintosc is also the frequency for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). the lfintosc is enabled by selecting 31 khz (ircf<3:0> bits of the osccon register = 000) as the system clock source (scs bits of the osccon register = 1x ), or when any of the following are enabled: configure the ircf<3:0> bits of the osccon register for the desired lf frequency, and fosc<2:0> = 100 , or set the system clock source (scs) bits of the osccon register to 1x peripherals that use the lfintosc are: power-up timer (pwrt) watchdog timer (wdt) fail-safe clock monitor (fscm) the low-frequency internal oscillator ready bit (lfiofr) of the oscstat register indicates when the lfintosc is running. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 54 ? 2011-2015 microchip technology inc. 5.2.2.3 internal oscillator frequency selection the system clock speed can be selected via software using the internal oscillator frequency select bits ircf<3:0> of the osccon register. the outputs of the 16 mhz hfintosc and lfintosc connects to a postscaler and multiplexer (see figure 5-1 ). the internal oscillator frequency select bits ircf<3:0> of the osccon register select the frequency output of the internal oscillators. one of the following frequencies can be selected via software: 16 mhz 8 mhz 4 mhz 2 mhz 1 mhz 500 khz (default after reset) 250 khz 125 khz 62.5 khz 31.25 khz 31 khz (lfintosc) the ircf<3:0> bits of the osccon register allow duplicate selections for some frequencies. these dupli- cate choices can offer system design trade-offs. lower power consumption can be obtained when changing oscillator sources for a given frequency. faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 5.2.2.4 internal oscillator clock switch timing when switching between the hfintosc and the lfintosc, the new oscillator may already be shut down to save power (see figure 5-7 ). if this is the case, there is a delay after the ircf<3:0> bits of the osccon register are modified before the frequency selection takes place. the oscstat register will reflect the current active status of the hfintosc and lfintosc oscillators. the sequence of a frequency selection is as follows: 1. ircf<3:0> bits of the osccon register are modified. 2. if the new clock is shut down, a clock start-up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. the current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. the new clock is now active. 6. the oscstat register is updated as required. 7. clock switch is complete. see figure 5-7 for more details. if the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. clock switching time delays are shown in table 5-1 . start-up delay specifications are located in the oscillator tables of section 25.0 ?electrical specifications? note: following any reset, the ircf<3:0> bits of the osccon register are set to 0111 and the frequency selection is set to 500 khz. the user can modify the ircf bits to select a different frequency. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 55 pic16(l)f1526/7 figure 5-7: internal oscillator switch timing hfintosc lfintosc ircf <3:0> system clock hfintosc lfintosc ircf <3:0> system clock ?? 0 ?? 0 ?? 0 ?? 0 oscillator delay (1) 2-cycle sync running 2-cycle sync running hfintosc lfintosc (fscm and wdt disabled) hfintosc lfintosc (either fscm or wdt enabled) lfintosc hfintosc ircf <3:0> system clock = 0 ? 0 oscillator delay (1) 2-cycle sync running lfintosc hfintosc lfintosc turns off unless wdt or fscm is enabled note: see tab le 5 - 1 , oscillator switching delays for more information. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 56 ? 2011-2015 microchip technology inc. 5.3 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bits of the osccon register. the following clock sources can be selected using the scs bits: default system oscillator determined by fosc bits in configuration words secondary oscillator 32 khz crystal internal oscillator block (intosc) 5.3.1 system clock select (scs) bits the system clock select (scs) bits of the osccon register selects the system clock source that is used for the cpu and peripherals. when the scs bits of the osccon register = 00 , the system clock source is determined by value of the fosc<2:0> bits in the configuration words. when the scs bits of the osccon register = 01 , the system clock source is the secondary oscillator. when the scs bits of the osccon register = 1x , the system clock source is chosen by the internal oscillator frequency selected by the ircf<3:0> bits of the osccon register. after a reset, the scs bits of the osccon register are always cleared. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscil- lator delays are shown in table 5-1 . 5.3.2 oscillator start-up timer status (osts) bit the oscillator start-up timer status (osts) bit of the oscstat register indicates whether the system clock is running from the external clock source, as defined by the fosc<2:0> bits in the configuration words, or from the internal clock source. in particular, osts indicates that the oscillator start-up timer (ost) has timed out for lp, xt or hs modes. the ost does not reflect the status of the secondary oscillator. 5.3.3 secondary oscillator the secondary oscillator is a separate crystal oscillator associated with the timer1 peripheral. it is optimized for timekeeping operations with a 32.768 khz crystal connected between the sosco and sosci device pins. the secondary oscillator is enabled using the soscen control bit in the txcon register. see section 18.0 ?timer1/3/5 module with gate control? for more information about the timer1 peripheral. 5.3.4 secondary oscillator ready (soscr) bit the user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. the secondary oscillator ready (soscr) bit of the oscstat register indicates whether the secondary oscillator is ready to be used. after the soscr bit is set, the scs bits can be configured to select the secondary oscillator. 5.3.5 clock switching before sleep when clock switching from an old clock to a new clock, prior to entering sleep mode, it is necessary to confirm that the switch is complete before the sleep instruction is executed. failure to do so may result in an incomplete switch and consequential loss of the system clock altogether. clock switching is confirmed by monitoring the clock status bits in the oscstat register. switch confirmation can be accomplished by sensing that the ready bit for the new clock is set or the ready bit for the old clock is cleared. for example, when switching between the internal oscillator with the pll and the internal oscillator without the pll, monitor the pllr bit. when pllr is set, the switch to 32 mhz operation is complete. conversely, when pllr is cleared the switch from the 32 mhz operation to the selected internal clock is complete. note: any automatic clock switch, which may occur from two-speed start-up or fail-safe clock monitor, does not update the scs bits of the osccon register. the user can monitor the osts bit of the oscstat register to determine the current system clock source. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 57 pic16(l)f1526/7 5.4 two-speed clock start-up mode two-speed start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. in applications that make heavy use of the sleep mode, two-speed start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. this mode allows the application to wake-up from sleep, perform a few instructions using the intosc internal oscillator block as the clock source and go back to sleep without waiting for the external oscillator to become stable. two-speed start-up provides benefits when the oscillator module is configured for lp, xt or hs modes. the oscillator start-up timer (ost) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. if the oscillator module is configured for any mode other than lp, xt or hs mode, then two-speed start-up is disabled. this is because the external clock oscillator does not require any stabilization time after por or an exit from sleep. if the ost count reaches 1024 before the device enters sleep mode, the osts bit of the oscstat reg- ister is set and program execution switches to the external oscillator. however, the system may never operate from the external oscillator if the time spent awake is very short. 5.4.1 two-speed start-up mode configuration two-speed start-up mode is configured by the following settings: ieso (of the configuration words) = 1 ; internal/external switchover bit (two-speed start-up mode enabled). scs (of the osccon register) = 00 . fosc<2:0> bits in the configuration words configured for lp, xt or hs mode. two-speed start-up mode is entered after: power-on reset (por) and, if enabled, after power-up timer (pwrt) has expired, or wake-up from sleep. table 5-1: oscillator switching delays note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit of the oscstat register to remain clear. switch from switch to oscillator delay any clock source lfintosc one cycle of each clock source hfintosc 2 ? s (approx.) ech, ecm, ecl, extrc 2 cycles lp, xt, hs 1024 clock cycles (ost) secondary oscillator 1024 secondary oscillator cycles downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 58 ? 2011-2015 microchip technology inc. 5.4.2 two-speed start-up sequence 1. wake-up from power-on reset or sleep. 2. instructions begin execution by the internal oscillator at the frequency set in the ircf<3:0> bits of the osccon register. 3. ost enabled to count 1024 clock cycles. 4. ost timed out, wait for falling edge of the internal oscillator. 5. osts is set. 6. system clock held low until the next falling edge of new clock (lp, xt or hs mode). 7. system clock is switched to external clock source. 5.4.3 checking two-speed clock status checking the state of the osts bit of the oscstat register will confirm if the microcontroller is running from the external clock source, as defined by the fosc<2:0> bits in the configuration words, or the internal oscillator. figure 5-8: two-speed start-up 0 1 1022 1023 pc + 1 t ost t intosc osc1osc2 program counter system clock pc - n pc downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 59 pic16(l)f1526/7 5.5 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue operating should the external oscillator fail. the fscm can detect oscillator failure any time after the oscillator start-up timer (ost) has expired. the fscm is enabled by setting the fcmen bit in the configuration words. the fscm is applicable to all external oscillator modes (lp, xt, hs, ec, rc and secondary oscillator). figure 5-9: fscm block diagram 5.5.1 fail-safe detection the fscm module detects a failed oscillator by comparing the external oscillator to the fscm sample clock. the sample clock is generated by dividing the lfintosc by 64. see figure 5-9 . inside the fail detector block is a latch. the external clock sets the latch on each falling edge of the external clock. the sample clock clears the latch on each rising edge of the sample clock. a failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 fail-safe operation when the external clock fails, the fscm switches the device clock to an internal clock source and sets the bit flag osfif of the pir2 register. setting this flag will generate an interrupt if the osfie bit of the pie2 register is also set. the device firmware can then take steps to mitigate the problems that may arise from a failed clock. the system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. the internal clock source chosen by the fscm is determined by the ircf<3:0> bits of the osccon register. this allows the internal oscillator to be configured before a failure occurs. 5.5.3 fail-safe condition clearing the fail-safe condition is cleared after a reset, executing a sleep instruction or changing the scs bits of the osccon register. when the scs bits are changed, the ost is restarted. while the ost is running, the device continues to operate from the intosc selected in osccon. when the ost times out, the fail-safe condition is cleared after successfully switching to the external clock source. the osfif bit should be cleared prior to switching to the external clock source. if the fail-safe condition still exists, the osfif flag will again become set by hardware. 5.5.4 reset or wake-up from sleep the fscm is designed to detect an oscillator failure after the oscillator start-up timer (ost) has expired. the ost is used after waking up from sleep and after any type of reset. the ost is not used with the ec or rc clock modes so that the fscm will be active as soon as the reset or wake-up has completed. when the fscm is enabled, the two-speed start-up is also enabled. therefore, the device will always be executing code while the ost is operating. external lfintosc 64 s r q 31 khz (~32 ? s) 488 hz (~2 ms) clock monitor latch clock failure detected oscillator clock q sample clock note: due to the wide range of oscillator start-up times, the fail-safe circuit is not active during oscillator start-up (i.e., after exiting reset or sleep). after an appropriate amount of time, the user should check the status bits in the oscstat register to verify the oscillator start-up and that the system clock switchover has successfully completed. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 60 ? 2011-2015 microchip technology inc. figure 5-10: fscm timing diagram oscfif system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q) te s t test test clock monitor output downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 61 pic16(l)f1526/7 5.6 register definitions: oscillator control register 5-1: osccon: os cillator control register u-0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-0/0 r/w-0/0 ircf<3:0> scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6-3 ircf<3:0>: internal oscillator frequency select bits 1111 =16mhz 1110 =8mhz 1101 =4mhz 1100 =2mhz 1011 =1mhz 1010 =500khz (1) 1001 =250khz (1) 1000 =125khz (1) 0111 = 500 khz (default upon reset) 0110 =250khz 0101 =125khz 0100 =62.5khz 001x =31.25khz 000x =31khz lf bit 2 unimplemented: read as 0 bit 1-0 scs<1:0>: system clock select bits 1x = internal oscillator block 01 = secondary oscillator 00 = clock determined by fosc<2:0> in configuration words. note 1: duplicate frequency derived from hfintosc. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 62 ? 2011-2015 microchip technology inc. table 5-2: summary of registers asso ciated with clock sources table 5-3: summary of configuration word wi th clock sources register 5-2: oscstat: oscillator status register r-1/q u-0 r-q/q r-0/q u-0 u-0 r-0/0 r-0/q soscr osts hfiofr lfiofr hfiofs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = conditional bit 7 soscr: secondary oscillator ready bit if so scen = 1 : 1 = secondary oscillator is ready 0 = secondary oscillator is not ready if so scen = 0 : 1 = timer1 clock source is always ready bit 6 unimplemented: read as 0 bit 5 osts: oscillator start-up timer status bit 1 = running from the clock defined by the fosc<2:0> bits of the configuration words 0 = running from an internal oscillator (fosc<2:0> = 100 ) bit 4 hfiofr: high-frequency internal oscillator ready bit 1 = hfintosc is ready 0 = hfintosc is not ready bit 3-2 unimplemented: read as 0 bit 1 lfiofr: low-frequency internal oscillator ready bit 1 = lfintosc is ready 0 = lfintosc is not ready bit 0 hfiofs: high-frequency internal oscillator stable bit 1 = hfintosc 16 mhz oscillator is stable and is driving the intosc 0 = hfintosc 16 mhz is not stable, the start-up oscillator is driving intosc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon ircf<3:0> s c s < 1 : 0 >6 1 oscstat soscr osts hfiofr lfiofr hfiofs 62 pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 78 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync tmr1on 168 legend: = unimplemented location, read as 0 . shaded cells are not used by clock sources. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 fcmen ieso clkouten boren<1:0> 43 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: = unimplemented location, read as 0 . shaded cells are not used by clock sources. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 63 pic16(l)f1526/7 6.0 resets there are multiple ways to reset this device: power-on reset (por) brown-out reset (bor) low-power brown-out reset (lpbor) mclr reset wdt reset reset instruction stack overflow stack underflow programming mode exit to a l l o w v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a bor or por event. a simplified block diagram of the on-chip reset circuit is shown in figure 6-1 . figure 6-1: simplified block di agram of on-chip reset circuit note 1: see table for bor active conditions. device reset power-on reset wdt time-out brown-out reset lpbor reset reset instruction mclre sleep bor active (1) pwrt r done pwrte lfintosc v dd icsp programming mode exit stack pointer downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 64 ? 2011-2015 microchip technology inc. 6.1 power-on reset (por) the por circuit holds the device in reset until v dd has reached an acceptable level for minimum operation. slow rising v dd , fast operating speeds or analog performance may require greater than minimum v dd . the pwrt, bor or mclr features can be used to extend the start-up period until all device operation conditions have been met. 6.1.1 power-up timer (pwrt) the power-up timer provides a nominal 64 ms time-out on por or brown-out reset. the device is held in reset as long as pwrt is active. the pwrt delay allows additional time for the v dd to rise to an acceptable level. the power-up timer is enabled by clearing the pwrte bit in configuration words. the power-up timer starts after the release of the por and bor. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 6.2 brown-out reset (bor) the bor circuit holds the device in reset when v dd reaches a selectable minimum level. between the por and bor, complete voltage range coverage for execution protection can be implemented. the brown-out reset module has four operating modes controlled by the boren<1:0> bits in configuration words. the four operating modes are: bor is always on bor is off when in sleep bor is controlled by software bor is always off refer to tab le for more information. the brown-out reset voltage level is selectable by configuring the borv bit in configuration words. a v dd noise rejection filter prevents the bor from triggering on small events. if v dd falls below v bor for a duration greater than parameter t bordc , the device will reset. see figure 6-2 for more information. 6.2.1 bor is always on when the boren bits of configuration words are programmed to 11 , the bor is always on. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is active during sleep. the bor does not delay wake-up from sleep. 6.2.2 bor is off in sleep when the boren bits of configuration words are programmed to 10 , the bor is on, except in sleep. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is not active during sleep. the device wake-up will be delayed until the bor is ready. 6.2.3 bor controlled by software when the boren bits of configuration words are programmed to 01 , the bor is controlled by the sboren bit of the borcon register. the device start-up is not delayed by the bor ready condition or the v dd level. bor protection begins as soon as the bor circuit is ready. the status of the bor circuit is reflected in the borrdy bit of the borcon register. bor protection is unchanged by sleep. table 6-1: bor operating modes boren<1:0> sboren device mode bor mode instruction execution upon: release of por or wake-up from sleep 11 x x active waits for bor ready (1) (borrdy = 1 ) 10 x awake active waits for bor ready (borrdy = 1 ) sleep disabled 01 1 x active waits for bor ready (1) (borrdy = 1 ) 0 x disabled begins immediately (borrdy = x ) 00 x x disabled note 1: in these specific cases, release of por and wake-up from sleep, there is no delay in start-up. the bor ready flag, (borrdy = 1 ), will be set before the cpu is ready to execute instructions because the bor circuit is forced on by the boren<1:0> bits. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 65 pic16(l)f1526/7 figure 6-2: brown -out situations 6.3 register definitions: bor control register 6-1: borcon: brown-o ut reset control register r/w-1/u r/w-0/u u-0 u-0 u-0 u-0 u-0 r-q/u sboren borfs b o r r d y bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other res ets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 sboren: software brown-out reset enable bit (1) if boren <1:0> ? 01 : sboren is read/write, but has no effect on the bor. if boren <1:0> = 01 : 1 = bor enabled 0 = bor disabled bit 6 borfs: brown-out reset fast start bit (1) if boren<1:0> = 11 (always on) or boren<1:0> = 00 (always off) borfs is read/write, but has no effect. if boren <1:0> = 10 (disabled in sleep) or boren<1:0> = 01 (under software control): 1 = band gap is forced on always (covers sleep/wake-up/operating cases) 0 = band gap operates normally, and may turn off bit 5-1 unimplemented: read as 0 bit 0 borrdy: brown-out reset circuit ready status bit 1 = the brown-out reset circuit is active 0 = the brown-out reset circuit is inactive note 1: boren<1:0> bits are located in configuration words. t pwrt (1) v bor v dd internal reset v bor v dd internal reset t pwrt (1) < t pwrt t pwrt (1) v bor v dd internal reset note 1: t pwrt delay only if pwrte bit is programmed to 0 . downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 66 ? 2011-2015 microchip technology inc. 6.4 low-power brown-out reset (lpbor) the low-power brown-out reset (lpbor) is an essential part of the reset subsystem. refer to figure 6-1 to see how the bor interacts with other modules. the lpbor is used to monitor the external v dd pin. when too low of a voltage is detected, the device is held in reset. when this occurs, a register bit (bor ) is changed to indicate that a bor reset has occurred. the same bit is set for both the bor and the lpbor. refer to register 6-2 . 6.4.1 enabling lpbor the lpbor is controlled by the l pbor bit of configuration words. when the device is erased, the lpbor module defaults to disabled. 6.4.1.1 lpbor module output the output of the lpbor module is a signal indicating whether or not a reset is to be asserted. this signal is ord together with the reset signal of the bor module to provide the generic bor signal, which goes to the pcon register and to the power control block. 6.5 mclr the mclr is an optional external input that can reset the device. the mclr function is controlled by the mclre bit of configuration words and the lvp bit of configuration words ( table 6-2 ). 6.5.1 mclr enabled when mclr is enabled and the pin is held low, the device is held in reset. the mclr pin is connected to v dd through an internal weak pull-up. the device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. 6.5.2 mclr disabled when mclr is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. see section register 12-19: ?porte: porte register? for more information. 6.6 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register are changed to indicate the wdt reset. see section 10.0 ?watchdog timer (wdt)? for more information. 6.7 reset instruction a reset instruction will cause a device reset. the ri bit in the pcon register will be set to 0 . see ta b l e 6 - 4 for default conditions after a reset instruction has occurred. 6.8 stack overflow/underflow reset the device can reset when the stack overflows or underflows. the stkovf or stkunf bits of the pcon register indicate the reset condition. these resets are enabled by setting the stvren bit in configuration words. see section 3.7.2 ?overflow/underflow reset? for more information. 6.9 programming mode exit upon exit of programming mode, the device will behave as if a por had just occurred. 6.10 power-up timer the power-up timer optionally delays device execution after a bor or por event. this timer is typically used to allow v dd to stabilize before allowing the device to start running. the power-up timer is controlled by the pwrte bit of configuration words. 6.11 start-up sequence upon the release of a por or bor, the following must occur before the device will begin executing: 1. power-up timer runs to completion (if enabled). 2. oscillator start-up timer runs to completion (if required for oscillator source). 3. mclr must be released (if enabled). the total time-out will vary based on oscillator configu- ration and power-up timer configuration. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information. the power-up timer and oscillator start-up timer run independently of mclr reset. if mclr is kept low long enough, the power-up timer and oscillator start-up timer will expire. upon bringing mclr high, the device will begin execution immediately (see figure 6-3 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. table 6-2: mclr configuration mclre lvp mclr 00 disabled 10 enabled x1 enabled note: a reset does not drive the mclr pin low. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 67 pic16(l)f1526/7 figure 6-3: reset start-up sequence t ost t mclr t pwrt v dd internal por power-up timer mclr internal reset oscillator modes oscillator start-up timer oscillator f osc internal oscillator oscillator f osc external clock (ec) clkin f osc external crystal downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 68 ? 2011-2015 microchip technology inc. 6.12 determining the cause of a reset upon any reset, multiple bits in the status and pcon register are updated to indicate the cause of the reset. ta b l e 6 - 3 and tab l e 6 - 4 show the reset conditions of these registers. table 6-3: reset status bits and their significance table 6-4: reset condition for special registers stkovf stkunf rwdt rmclr ri por bor to pd condition 0 0 1 1 10 x11 power-on reset 0 0 1 1 10 x0x illegal, to is set on por 0 0 1 1 10 xx0 illegal, pd is set on por 0 0 u 1 1u 011 brown-out reset u u 0 u uu u0u wdt reset u u u u uu u00 wdt wake-up from sleep u u u u uu u10 interrupt wake-up from sleep u u u 0 uu uuu mclr reset during normal operation u u u 0 uu u10 mclr reset during sleep u u u u 0 u u u u reset instruction executed 1 u u u uu uuu stack overflow reset (stvren = 1 ) u 1 u u uu uuu stack underflow reset (stvren = 1 ) condition program counter status register pcon register power-on reset 0000h ---1 1000 00-1 110x mclr reset during normal operation 0000h ---u uuuu uu-u 0uuu mclr reset during sleep 0000h ---1 0uuu uu-u 0uuu wdt reset 0000h ---0 uuuu uu-0 uuuu wdt wake-up from sleep pc + 1 ---0 0uuu uu-u uuuu brown-out reset 0000h ---1 1uuu 00-1 11u0 interrupt wake-up from sleep pc + 1 (1) ---1 0uuu uu-u uuuu reset instruction executed 0000h ---u uuuu uu-u u0uu stack overflow reset (stvren = 1 ) 0000h ---u uuuu 1u-u uuuu stack underflow reset (stvren = 1 ) 0000h ---u uuuu u1-u uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as 0 . note 1: when the wake-up is due to an interrupt and global enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 69 pic16(l)f1526/7 6.13 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: power-on reset (por ) brown-out reset (bor ) reset instruction reset (ri ) mclr reset (rmclr ) watchdog timer reset (rwdt ) stack underflow reset (stkunf) stack overflow reset (stkovf) the pcon register bits are shown in register 6-2 . 6.14 register definitions: power control register 6-2: pcon: power control register r/w/hs-0/q r/w/hs-0/q u-0 r/w/hc-1/q r/w/ hc-1/q r/w/hc-1/q r/w/hc-q/u r/w/hc-q/u stkovf stkunf r wdt rmclr ri por bor bit 7 bit 0 legend: hc = bit is cleared by hardware hs = bit is set by hardware r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 stkovf: stack overflow flag bit 1 = a stack overflow occurred 0 = a stack overflow has not occurred or cleared by firmware bit 6 stkunf: stack underflow flag bit 1 = a stack underflow occurred 0 = a stack underflow has not occurred or cleared by firmware bit 5 unimplemented: read as 0 bit 4 r wdt : watchdog timer reset flag bit 1 = a watchdog timer reset has not occurred or set to 1 by firmware 0 = a watchdog timer reset has occurred (cleared by hardware) bit 3 rmclr : mclr reset flag bit 1 = a mclr reset has not occurred or set to 1 by firmware 0 = a mclr reset has occurred (cleared by hardware) bit 2 ri : reset instruction flag bit 1 = a reset instruction has not been executed or set to 1 by firmware 0 = a reset instruction has been executed (cleared by hardware) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 70 ? 2011-2015 microchip technology inc. table 6-5: summary of registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page borcon sboren borfs borrdy 65 pcon stkovf stkunf r wdt rmclr ri por bor 69 status t o pd z dc c 21 wdtcon wdtps<4:0> swdten 93 legend: = unimplemented bit, read as 0 . shaded cells are not used by resets. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 71 pic16(l)f1526/7 7.0 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. this chapter contains the following information for interrupts: operation interrupt latency interrupts during sleep int pin automatic context saving many peripherals produce interrupts. refer to the corresponding chapters for details. a block diagram of the interrupt logic is shown in figure 7-1 . figure 7-1: interrupt logic tmr0if tmr0ie intf inte iocif iocie interrupt to cpu wake-up (if in sleep mode) gie (tmr1if) pir1<0> pirn<7> peie (tmr1ie) pie1<0> peripheral interrupts pien<7> downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 72 ? 2011-2015 microchip technology inc. 7.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: gie bit of the intcon register interrupt enable bit(s) for the specific interrupt event(s) peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the piex register) the intcon and pirx registers record individual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: current prefetched instruction is flushed gie bit is cleared current program counter (pc) is pushed onto the stack critical registers are automatically saved to the shadow registers (see section 7.5 ?automatic context saving? ) pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupts operation, refer to its peripheral chapter. 7.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is three or four instruction cycles. for asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. see figure 7-2 and figure 7-3 for more details. note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 73 pic16(l)f1526/7 figure 7-2: interrupt latency q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkr pc 0004h 0005h pc inst(0004h) nop gie q1 q2 q3 q4 q1 q2 q3 q4 1 cycle instruction at pc pc inst(0004h) nop 2 cycle instruction at pc fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc execute interrupt inst(pc) interrupt sampled during q1 inst(pc) pc-1 pc+1 nop pc new pc/ pc+1 0005h pc-1 pc+1/fsr addr 0004h nop interrupt gie interrupt inst(pc) nop nop fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc interrupt inst(pc) nop nop nop inst(0005h) execute execute execute downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 74 ? 2011-2015 microchip technology inc. figure 7-3: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf gie instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) forced nop inst (pc) inst (pc + 1) inst (pc C 1) inst (0004h) forced nop inst (pc) note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-5 t cy . synchronous latency = 3-4 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout not available in all oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 25.0 ?electrical specifications? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1) downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 75 pic16(l)f1526/7 7.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to the section 8.0 ?power-down mode (sleep)? for more details. 7.4 int pin the int pin can be used to generate an asynchronous edge-triggered interrupt. this interrupt is enabled by setting the inte bit of the intcon register. the intedg bit of the option_reg register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the intcon register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 automatic context saving upon entering an interrupt, the return pc address is saved on the stack. additionally, the following registers are automatically saved in the shadow registers: w register status register (except for to and pd ) bsr register fsr registers pclath register upon exiting the interrupt service routine, these registers are automatically restored. any modifications to these registers during the isr will be lost. if modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the isr. the shadow registers are available in bank 31 and are readable and writable. depending on the users application, other registers may also need to be saved. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 76 ? 2011-2015 microchip technology inc. 7.6 register definitions: interrupt control register 7-1: intcon: interrupt control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 gie peie tmr0ie inte iocie tmr0if intf iocif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 gie: global interrupt enable bit 1 = enables all active interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all active peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 iocie: interrupt-on-change interrupt enable bit 1 = enables the interrupt-on-change interrupt 0 = disables the interrupt-on-change interrupt bit 2 tmr0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed 0 = tmr0 register did not overflow bit 1 intf: int external interrupt flag bit 1 = the int external interrupt occurred 0 = the int external interrupt did not occur bit 0 iocif: interrupt-on-change interrupt flag bit (1) 1 = when at least one of the interrupt-on-change pins changed state 0 = none of the interrupt-on-change pins have changed state note 1: the iocif flag bit is read-only and cleared when all the interrupt-on-change flags in the iocbf register have been cleared by software. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 77 pic16(l)f1526/7 register 7-2: pie1: peripheral interrupt enable register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr1gie adie rc1ie tx1ie ssp1ie ssp2ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 tmr1gie: timer1 gate interrupt enable bit 1 = enables the timer1 gate acquisition interrupt 0 = disables the timer1 gate acquisition interrupt bit 6 adie: analog-to-digital converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 rc1ie: usart1 receive interrupt enable bit 1 = enables the usart1 receive interrupt 0 = disables the usart1 receive interrupt bit 4 tx1ie: usart1 transmit interrupt enable bit 1 = enables the usart1 transmit interrupt 0 = disables the usart1 transmit interrupt bit 3 ssp1ie: synchronous serial port (mssp1) interrupt enable bit 1 = enables the mssp1 interrupt 0 = disables the mssp1 interrupt bit 2 ssp2ie: synchronous serial port (mssp2) interrupt enable bit 1 = enables the mssp2 interrupt 0 = disables the mssp2 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 78 ? 2011-2015 microchip technology inc. register 7-3: pie2: peripheral interrupt enable register 2 u-0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 ad2ie bcl1ie bcl2ie tmr4ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 ad2ie: analog-to-digital converter (adc2) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5-4 unimplemented: read as 0 bit 3 bcl1ie: mssp1 bus collision interrupt enable bit 1 = enables the mssp1 bus collision interrupt 0 = disables the mssp1 bus collision interrupt bit 2 bcl2ie: mssp2 bus collision interrupt enable bit 1 = enables the mssp2 bus collision interrupt 0 = disables the mssp2 bus collision interrupt bit 1 tmr4ie: tmr4 to pr4 match interrupt enable bit 1 = enables the timer8 to pr4 match interrupt 0 = disables the timer8 to pr4 match interrupt bit 0 unimplemented: read as 0 note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 79 pic16(l)f1526/7 register 7-4: pie3: peripheral interrupt enable register 3 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 ccp6ie: ccp6 interrupt enable bit 1 = enables the ccp6 interrupt 0 = disables the ccp6 interrupt bit 6 ccp5ie: ccp5 interrupt enable bit 1 = enables the ccp5 interrupt 0 = disables the ccp5 interrupt bit 5 ccp4ie: ccp4 interrupt enable bit 1 = enables the ccp4 interrupt 0 = disables the ccp4 interrupt bit 4 ccp3ie: ccp3 interrupt enable bit 1 = enables the ccp3 interrupt 0 = disables the ccp3 interrupt bit 3 tmr6ie: tmr6 to pr6 match interrupt enable bit 1 = enables the tmr6 to pr6 match interrupt 0 = disables the tmr6 to pr6 match interrupt bit 2 tmr5ie: timer5 overflow interrupt enable bit 1 = enables the timer5 overflow interrupt 0 = disables the timer5 overflow interrupt bit 1 tmr4ie: tmr4 to pr4 match interrupt enable bit 1 = enables the tmr4 to pr4 match interrupt 0 = disables the tmr4 to pr4 match interrupt bit 0 tmr3ie: timer3 overflow interrupt enable bit 1 = enables the timer3 overflow interrupt 0 = disables the timer3 overflow interrupt note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 80 ? 2011-2015 microchip technology inc. register 7-5: pie4: peripheral interrupt enable register 4 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 ccp10ie: ccp10 interrupt enable bit 1 = enables the ccp10 interrupt 0 = disables the ccp10 interrupt bit 6 ccp9ie: ccp9 interrupt enable bit 1 = enables the ccp9 interrupt 0 = disables the ccp9 interrupt bit 5 rc2ie: usart2 receive interrupt enable bit 1 = enables the usart2 receive interrupt 0 = disables the usart2 receive interrupt bit 4 tx2ie: usart2 transmit interrupt enable bit 1 = enables the usart2 transmit interrupt 0 = disables the usart2 transmit interrupt bit 3 ccp8ie: ccp8 interrupt enable bit 1 = enables the ccp8 interrupt 0 = disables the ccp8 interrupt bit 2 ccp7ie: ccp7 interrupt enable bit 1 = enables the ccp7 interrupt 0 = disables the ccp7 interrupt bit 1 bcl2ie: mssp2 bus collision interrupt enable bit 1 = enables the mssp2 bus collision interrupt 0 = disables the mssp2 bus collision interrupt bit 0 ssp2ie: synchronous serial port (mssp2) interrupt enable bit 1 = enables the mssp2 interrupt 0 = disables the mssp2 interrupt note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 81 pic16(l)f1526/7 register 7-6: pir1: peripheral interrupt request register 1 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 tmr1gif: timer1 gate interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 adif: adc converter interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 rc1if: usart1 receive interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 tx1if: usart1 transmit interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3 ssp1if: synchronous serial port (mssp1) interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 ccp1if: ccp1 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1 tmr2if: timer2 to pr2 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 82 ? 2011-2015 microchip technology inc. register 7-7: pir2: peripheral interrupt request register 2 u-0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 a d 2 i f bcl1if bcl2if tmr4if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 ad2if: timer5 gate interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5-4 unimplemented: read as 0 bit 3 bcl1if: mssp1 bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 bcl2if: mssp2 bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1 tmr4if: timer4 to pr4 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 unimplemented: read as 0 note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 83 pic16(l)f1526/7 register 7-8: pir3: peripheral interrupt request register 3 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 ccp6if: ccp6 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 ccp5if: ccp5 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 ccp4if: ccp4 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 ccp3if: ccp3 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3 tmr6if: tmr6 to pr6 match interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 tmr5if: timer5 overflow interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1 tmr4if: tmr4 to pr4 match interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 tmr3if: timer3 overflow interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 84 ? 2011-2015 microchip technology inc. register 7-9: pir4: peripheral interrupt request register 4 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 ccp10if: ccp10 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 ccp9if: ccp9 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 rc2if: usart2 receive interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 tx2if: usart2 transmit interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3 ccp8if: ccp8 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 ccp7if: ccp7 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1 bcl2if: mssp2 bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 ssp2if: synchronous serial port (mssp2) interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 85 pic16(l)f1526/7 table 7-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 iocbf iocbf7 iocbf6iocbf5iocbf4iocbf3iocbf2iocbf1iocbf0 137 iocbn iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 137 iocbp iocbp7 iocbp6 iocbp5 iocb p4 iocbp3 iocbp2 iocbp1 iocbp0 137 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 158 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ssp2ie tmr2ie tmr1ie 77 pie2 a d 2 i e bcl1ie bcl2ie tmr4ie 78 pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 79 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif ad1if rcif txif ssp1if ssp2if tmr2if tmr1if 81 pir2 a d 2 i f bcl1if bcl2if tmr4if 82 pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 83 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 legend: = unimplemented locations read as 0 . shaded cells are not used by interrupts. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 86 ? 2011-2015 microchip technology inc. 8.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled for operation during sleep. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is disabled. 5. 31 khz lfintosc is unaffected and peripherals that operate from it may continue operation in sleep. 6. timer1 and peripherals that operate from tim- er1 continue operation in sleep when the tim- er1 clock source selected is: lfintosc t1cki secondary oscillator 7. adc is unaffected, if the dedicated f rc oscillator is selected. 8. i/o ports maintain the status they had before sleep was executed (driving high, low or high-impedance). 9. resets other than wdt are not affected by sleep mode. refer to individual chapters for more details on periph- eral operation during sleep. to minimize current consumption, the following condi- tions should be considered: i/o pins should not be floating external circuitry sinking current from i/o pins internal circuitry sourcing current from i/o pins current draw from pins with internal weak pull-ups modules using 31 khz lfintosc modules using secondary oscillator i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching currents caused by floating inputs. examples of internal circuitry that might be sourcing current include modules such as the fvr modules. see section 14.0 ?fixed voltage reference (fvr)? for more information on these modules. 8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled 3. por reset 4. watchdog timer, if enabled 5. any external interrupt 6. interrupts by peripherals capable of running during sleep (see individual peripheral for more information) the first three events will cause a device reset. the last three events are considered a continuation of program execution. to determine whether a device reset or wake-up event occurred, refer to section 6.12 ?determining the cause of a reset? . when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will then call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 87 pic16(l)f1526/7 8.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop . - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction - sleep instruction will be completely exe- cuted - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . figure 8-1: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (4) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) forced nop pc + 2 0004h 0005h forced nop t ost (3) pc + 2 note 1: xt, hs or lp oscillator mode assumed. 2: clkout is shown here for timing reference. 3: t ost = 1024 t osc . this delay does not apply to ec, rc and intosc oscillator modes or two-speed start- up (if available). 4: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 88 ? 2011-2015 microchip technology inc. 8.2 low-power sleep mode the pic16f1526 device contains an internal low dropout (ldo) voltage regulator, which allows the device i/o pins to operate at voltages up to 5.5v while the internal device logic operates at a lower voltage. the ldo and its associated reference circuitry must remain active when the device is in sleep mode. the pic16f1526 allows the user to optimize the operating current in sleep, depending on the application requirements. a low-power sleep mode can be selected by setting the vregpm bit of the vregcon register. with this bit set, the ldo and reference circuitry are placed in a low-power state when the device is in sleep. 8.2.1 sleep current vs. wake-up time in the default operating mode, the ldo and reference circuitry remain in the normal configuration while in sleep. the device is able to exit sleep mode quickly since all circuits remain active. in low-power sleep mode, when waking up from sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. the low-power sleep mode is beneficial for applications that stay in sleep mode for long periods of time. the normal mode is beneficial for applications that need to wake from sleep quickly and frequently. 8.2.2 peripheral usage in sleep some peripherals that can operate in sleep mode will not operate properly with the low-power sleep mode selected. the ldo will remain in the normal power mode when those peripherals are enabled. the low-power sleep mode is intended for use with these peripherals: brown-out reset (bor) watchdog timer (wdt) external interrupt pin/interrupt-on-change pins timer1 (with external clock source) ccp (capture mode) note: the pic16lf1526/7 does not have a configurable low-power sleep mode. pic16lf1526/7 is an unregulated device and is always in the lowest power state when in sleep, with no wake-up time penalty. this device has a lower maximum v dd and i/o voltage than the pic16lf1526/7. see section 25.0 ?electrical specifications? for more information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 89 pic16(l)f1526/7 8.3 register definitions: voltage regulator control table 8-1: summary of registers as sociated with power-down mode register 8-1: vregcon: voltag e regulator control register (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-1/1 v r e g p m reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-2 unimplemented: read as 0 bit 1 vregpm: voltage regulator power mode selection bit 1 = low-power sleep mode enabled in sleep (2) draws lowest current in sleep, slower wake-up 0 = normal power mode enabled in sleep (2) draws higher current in sleep, faster wake-up bit 0 reserved: read as 1 . maintain this bit set. note 1: pic16f1526/7 only. 2: see section 25.0 ?electrical specifications? . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 iocbf iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 137 iocbn iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 137 iocbp iocbp7 iocbp6 iocbp5 iocbp4 iocbp3 iocbp2 iocbp1 iocbp0 137 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie2 osfie tmr5gie tmr3gie bclie tmr10ie tmr8ie ccp2ie 78 pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 79 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 83 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 status t o pd z dc c 21 vregcon (1) v r e g p m reserved 89 wdtcon wdtps<4:0> swdten 93 legend: = unimplemented, read as 0 . shaded cells are not used in power-down mode. note 1: pic16f1526/7 only. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 90 ? 2011-2015 microchip technology inc. 9.0 low dropout (ldo) voltage regulator the pic16f1526/7 has an internal low dropout regulator (ldo) which provides operation above 3.6v. the ldo regulates a voltage for the internal device logic while permitting the v dd and i/o pins to operate at a higher voltage. there is no user enable/disable control available for the ldo, it is always active. the pic16lf1526/7 operates at a maximum v dd of 3.6v and does not incorporate an ldo. a device i/o pin may be configured as the ldo voltage output, identified as the v cap pin. although not required, an external low-esr capacitor may be con- nected to the v cap pin for additional regulator stability. the vcapen bit of configuration words determines which pin is assigned as the v cap pin. refer to table 9-1 . on power-up, the external capacitor will load the ldo voltage regulator. to prevent erroneous operation, the device is held in reset while a constant current source charges the external capacitor. after the cap is fully charged, the device is released from reset. for more information on the constant current rate, refer to the ldo regulator characteristics table in section 25.0, electrical specifications . table 9-2: summary of conf iguration word with ldo table 9-1: vcapen select bit vcapen pin 0 rf0 1 no vcap name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config2 13:8 lvp debug l pbor borv stvren 45 7:0 vcapen (1) wrt<1:0> legend: = unimplemented locations read as 0 . shaded cells are not used by ldo. note 1: pic16f1526/7 only. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 91 pic16(l)f1526/7 10.0 watchdog timer (wdt) the watchdog timer is a system timer that generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the watchdog timer is typically used to recover the system from unexpected events. the wdt has the following features: independent clock source multiple operating modes - wdt is always on - wdt is off when in sleep - wdt is controlled by software - wdt is always off configurable time-out period is from 1 ms to 256 seconds (nominal) multiple reset conditions operation during sleep figure 10-1: watchdog ti mer block diagram lfintosc 23-bit programmable prescaler wdt wdt time-out wdtps<4:0> swdten sleep wdte<1:0> = 11 wdte<1:0> = 01 wdte<1:0> = 10 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 92 ? 2011-2015 microchip technology inc. 10.1 independent clock source the wdt derives its time base from the 31 khz lfintosc internal oscillator. time intervals in this chapter are based on a nominal interval of 1 ms. see section 25.0 ?electrical specifications? for the lfintosc tolerances. 10.2 wdt operating modes the watchdog timer module has four operating modes controlled by the wdte<1:0> bits in configuration words. see table 10-1 . 10.2.1 wdt is always on when the wdte bits of configuration words are set to 11 , the wdt is always on. wdt protection is active during sleep. 10.2.2 wdt is off in sleep when the wdte bits of configuration words are set to 10 , the wdt is on, except in sleep. wdt protection is not active during sleep. 10.2.3 wdt controlled by software when the wdte bits of configuration words are set to 01 , the wdt is controlled by the swdten bit of the wdtcon register. wdt protection is unchanged by sleep. see table 10-1 for more details. table 10-1: wdt operating modes 10.3 time-out period the wdtps bits of the wdtcon register set the time-out period from 1 ms to 256 seconds (nominal). after a reset, the default time-out period is 2 seconds. 10.4 clearing the wdt the wdt is cleared when any of the following condi- tions occur: any reset clrwdt instruction is executed device enters sleep device wakes up from sleep oscillator fail wdt is disabled oscillator start-up timer (ost) is running see table 10-2 for more information. 10.5 operation during sleep when the device enters sleep, the wdt is cleared. if the wdt is enabled during sleep, the wdt resumes counting. when the device exits sleep, the wdt is cleared again. the wdt remains clear until the ost, if enabled, completes. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information on the ost. when a wdt time-out occurs while the device is in sleep, no reset is generated. instead, the device wakes up and resumes operation. the to and pd bits in the status register are changed to indicate the event. the rwdt bit in the pcon register can also be used. see section 3.0 ?memory organization? and the status register ( register 3-1 ) for more information. wdte<1:0> swdten device mode wdt mode 11 x xa c t i v e 10 x awake active sleep disabled 01 1 xa c t i v e 0 x disabled 00 x x disabled table 10-2: wdt clearing conditions conditions wdt wdte<1:0> = 00 cleared wdte<1:0> = 01 and swdten = 0 wdte<1:0> = 10 and enter sleep clrwdt command oscillator fail detected exit sleep + system clock = sosc, extrc, intosc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost change intosc divider (ircf bits) unaffected downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 93 pic16(l)f1526/7 10.6 register definitions: watchdog control register 10-1: wdtcon: wat chdog timer control register u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 wdtps<4:0> swdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-1 wdtps<4:0>: watchdog timer period select bits (1) bit value = prescale rate 11111 = reserved. results in minimum interval (1:32) 10011 = reserved. results in minimum interval (1:32) 10010 = 1:8388608 (2 23 ) (interval 256s nominal) 10001 = 1:4194304 (2 22 ) (interval 128s nominal) 10000 = 1:2097152 (2 21 ) (interval 64s nominal) 01111 = 1:1048576 (2 20 ) (interval 32s nominal) 01110 = 1:524288 (2 19 ) (interval 16s nominal) 01101 = 1:262144 (2 18 ) (interval 8s nominal) 01100 = 1:131072 (2 17 ) (interval 4s nominal) 01011 = 1:65536 (interval 2s nominal) (reset value) 01010 = 1:32768 (interval 1s nominal) 01001 = 1:16384 (interval 512 ms nominal) 01000 = 1:8192 (interval 256 ms nominal) 00111 = 1:4096 (interval 128 ms nominal) 00110 = 1:2048 (interval 64 ms nominal) 00101 = 1:1024 (interval 32 ms nominal) 00100 = 1:512 (interval 16 ms nominal) 00011 = 1:256 (interval 8 ms nominal) 00010 = 1:128 (interval 4 ms nominal) 00001 = 1:64 (interval 2 ms nominal) 00000 = 1:32 (interval 1 ms nominal) bit 0 swdten: software enable/disable for watchdog timer bit if wdte<1:0> = 00 : this bit is ignored. if wdte<1:0> = 01 : 1 = wdt is turned on 0 = wdt is turned off if wdte<1:0> = 1x : this bit is ignored. note 1: times are approximate. wdt time is based on 31 khz lfintosc. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 94 ? 2011-2015 microchip technology inc. table 10-3: summary of registers associated with watchdog timer table 10-4: summary of configurat ion word with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon ircf<3:0> s c s < 1 : 0 > 61 status t o pd z dc c 21 wdtcon wdtps<4:0> swdten 93 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by watchdog timer . name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 fcmen ieso clkouten boren<1:0> 43 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: = unimplemented location, read as 0 . shaded cells are not used by watchdog timer. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 95 pic16(l)f1526/7 11.0 flash program memory control the flash program memory is readable and writable during normal operation over the full v dd range. program memory is indirectly addressed using special function registers (sfrs). the sfrs used to access program memory are: pmcon1 pmcon2 pmdatl pmdath pmadrl pmadrh when accessing the program memory, the pmdath:pmdatl register pair forms a 2-byte word that holds the 14-bit data for read/write, and the pmadrh:pmadrl register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. the flash program memory can be protected in two ways; by code protection (cp bit in configuration words) and write protection (wrt<1:0> bits in configuration words). code protection (cp = 0 ) (1) , disables access, reading and writing, to the flash program memory via external device programmers. code protection does not affect the self-write and erase functionality. code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all flash program memory, configuration bits and user ids. write protection prohibits self-write and erase to a portion or all of the flash program memory as defined by the bits wrt<1:0>. write protection does not affect a device programmers ability to read, write or erase the device. 11.1 pmadrl and pmadrh registers the pmadrh:pmadrl register pair can address up to a maximum of 32k words of program memory. when selecting a program address value, the msb of the address is written to the pmadrh register and the lsb is written to the pmadrl register. 11.1.1 pmcon1 and pmcon2 registers pmcon1 is the control register for flash program memory accesses. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared by hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation to occur. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a reset during normal operation. in these situations, following reset, the user can check the wrerr bit and execute the appropriate error handling routine. the pmcon2 register is a write-only register. attempting to read the pmcon2 register will return all 0 s. to enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the pmcon2 register. the required unlock sequence prevents inadvertent writes to the program memory write latches and flash program memory. 11.2 flash program memory overview it is important to understand the flash program memory structure for erase and programming operations. flash program memory is arranged in rows. a row consists of a fixed number of 14-bit program memory words. a row is the minimum size that can be erased by user software. after a row has been erased, the user can reprogram all or a portion of this row. data to be written into the program memory row is written to 14-bit wide data write latches. these write latches are not directly accessible to the user, but may be loaded via sequential writes to the pmdath:pmdatl register pair. see table 11-1 for erase row size and the number of write latches for flash program memory. note 1: code protection of the entire flash program memory array is enabled by clearing the cp bit of configuration words. note: if the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in ram prior to the erase. then, new data and retained data can be written into the write latches to reprogram the row of flash program memory. how- ever, any unprogrammed locations can be written without first erasing the row. in this case, it is not necessary to save and rewrite the other previously programmed locations. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 96 ? 2011-2015 microchip technology inc. 11.2.1 reading the flash program memory to read a program memory location, the user must: 1. write the desired address to the pmadrh:pmadrl register pair. 2. clear the cfgs bit of the pmcon1 register. 3. then, set control bit rd of the pmcon1 register. once the read control bit is set, the program memory flash controller will use the second instruction cycle to read the data. this causes the second instruction immediately following the bsf pmcon1,rd instruction to be ignored. the data is available in the very next cycle, in the pmdath:pmdatl register pair; therefore, it can be read as two bytes in the following instructions. pmdath:pmdatl register pair will hold this value until another read or until it is written to by the user. figure 11-1: flash program memory read flowchart table 11-1: flash memory organization by device device row erase (words) write latches (words) pic16(l)f1526 32 32 pic16(l)f1527 note: the two instructions following a program memory read are required to be nop s. this prevents the user from executing a two-cycle instruction on the next instruction after the rd bit is set. start read operation select program or configuration memory (cfgs) select word address (pmadrh:pmadrl) end read operation instruction fetched ignored nop execution forced instruction fetched ignored nop execution forced initiate read operation (rd = 1 ) data read now in pmdath:pmdatl downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 97 pic16(l)f1526/7 figure 11-2: flash program me mory read cycle execution example 11-1: flash program memory read q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr(pc + 1) executed here pc pc + 1 pmadrh,pmadrl pc+3 pc + 5 flash addr rd bit pmdath,pmdatl pc + 3 pc + 4 instr (pc + 1) instr(pc - 1) executed here instr(pc + 3) executed here instr(pc + 4) executed here flash data pmdath pmdatl register instr (pc) instr (pc + 3) instr (pc + 4) instruction ignored forced nop instr(pc + 2) executed here instruction ignored forced nop * this code block will read 1 word of program * memory at the memory address: prog_addr_hi : prog_addr_lo * data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select bank for pmcon registers movlw prog_addr_lo ; movwf pmadrl ; store lsb of address movlw prog_addr_hi ; movwl pmadrh ; store msb of address bcf pmcon1,cfgs ; do not select configuration space bsf pmcon1,rd ; initiate read nop ; ignored ( figure 11-2 ) nop ; ignored ( figure 11-2 ) movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 98 ? 2011-2015 microchip technology inc. 11.2.2 flash memory unlock sequence the unlock sequence is a mechanism that protects the flash program memory from unintended self-write programming or erasing. the sequence must be executed and completed without interruption to successfully complete any of the following operations: row erase load program memory write latches write of program memory write latches to pro- gram memory write of program memory write latches to user ids the unlock sequence consists of the following steps: 1. write 55h to pmcon2 2. write aah to pmcon2 3. set the wr bit in pmcon1 4. nop instruction 5. nop instruction once the wr bit is set, the processor will always force two nop instructions. when an erase row or program row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. when the operation is loading the program memory write latches, the processor will always force the two nop instructions and continue uninterrupted with the next instruction. since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. figure 11-3: flash program memory unlock sequence flowchart write 055h to pmcon2 start unlock sequence write 0aah to pmcon2 initiate write or erase operation (wr = 1 ) instruction fetched ignored nop execution forced end unlock sequence instruction fetched ignored nop execution forced downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 99 pic16(l)f1526/7 11.2.3 erasing flash program memory while executing code, program memory can only be erased by rows. to erase a row: 1. load the pmadrh:pmadrl register pair with any address within the row to be erased. 2. clear the cfgs bit of the pmcon1 register. 3. set the free and wren bits of the pmcon1 register. 4. write 55h, then aah, to pmcon2 (flash programming unlock sequence). 5. set control bit wr of the pmcon1 register to begin the erase operation. see example 11-2 . after the bsf pmcon1,wr instruction, the processor requires two cycles to set up the erase operation. the user must place two nop instructions immediately following the wr bit set instruction. the processor will halt internal operations for the typical 2 ms erase time. this is not sleep mode as the clocks and peripherals will continue to run. after the erase cycle, the processor will resume operation with the third instruction after the pmcon1 write instruction. figure 11-4: flash program memory erase flowchart disable interrupts (gie = 0 ) start erase operation select program or configuration memory (cfgs) select row address (pmadrh:pmadrl) select erase operation (free = 1 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end erase operation cpu stalls while erase operation completes (2ms typical) figure 11-3 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 100 ? 2011-2015 microchip technology inc. example 11-2: erasing one row of program memory ; this row erase routine assumes the following: ; 1. a valid address within the erase row is loaded in addrh:addrl ; 2. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrl movf addrl,w ; load lower 8 bits of erase address boundary movwf pmadrl movf addrh,w ; load upper 6 bits of erase address boundary movwf pmadrh bcf pmcon1,cfgs ; not configuration space bsf pmcon1,free ; specify an erase operation bsf pmcon1,wren ; enable writes movlw 55h ; start of required sequence to initiate erase movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin erase nop ; nop instructions are forced as processor starts nop ; row erase of program memory. ; ; the processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 101 pic16(l)f1526/7 11.2.4 writing to flash program memory program memory is programmed using the following steps: 1. load the address in pmadrh:pmadrl of the row to be programmed. 2. load each write latch with data. 3. initiate a programming operation. 4. repeat steps 1 through 3 until all data is written. before writing to program memory, the word(s) to be written must be erased or previously unwritten. pro- gram memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write. program memory can be written one or more words at a time. the maximum number of words written at one time is equal to the number of write latches. see figure 11-5 (row writes to program memory with 32 write latches) for more details. the write latches are aligned to the flash row address boundary defined by the upper 10-bits of pmadrh:pmadrl, (pmadrh<6:0>:pmadrl<7:5>) with the lower 5-bits of pmadrl, (pmadrl<4:0>) determining the write latch being loaded. write opera- tions do not cross these boundaries. at the completion of a program memory write operation, the data in the write latches is reset to contain 0x3fff. the following steps should be completed to load the write latches and program a row of program memory. these steps are divided into two parts. first, each write latch is loaded with data from the pmdath:pmdatl using the unlock sequence with lwlo = 1 . when the last word to be loaded into the write latch is ready, the lwlo bit is cleared and the unlock sequence executed. this initiates the programming operation, writing all the latches into flash program memory. 1. set the wren bit of the pmcon1 register. 2. clear the cfgs bit of the pmcon1 register. 3. set the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is 1 , the write sequence will only load the write latches and will not initiate the write to flash program memory. 4. load the pmadrh:pmadrl register pair with the address of the location to be written. 5. load the pmdath:pmdatl register pair with the program memory data to be written. 6. execute the unlock sequence ( section 11.2.2 ?flash memory unlock sequence? ). the write latch is now loaded. 7. increment the pmadrh:pmadrl register pair to point to the next location. 8. repeat steps 5 through 7 until all but the last write latch has been loaded. 9. clear the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is 0 , the write sequence will initiate the write to flash program memory. 10. load the pmdath:pmdatl register pair with the program memory data to be written. 11. execute the unlock sequence ( section 11.2.2 ?flash memory unlock sequence? ). the entire program memory latch content is now written to flash program memory. an example of the complete write sequence is shown in example 11-3 . the initial address is loaded into the pmadrh:pmadrl register pair; the data is loaded using indirect addressing. note: the special unlock sequence is required to load a write latch with data or initiate a flash programming operation. if the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. note: the program memory write latches are reset to the blank state (0x3fff) at the completion of every write or erase operation. as a result, it is not necessary to load all the program memory write latches. unloaded latches will remain in the blank state. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 102 ? 2011-2015 microchip technology inc. figure 11-5: block writes to flash program memory with 32 write latches pmdath pmdatl 7 5 0 7 0 6 8 14 14 14 write latch #31 1fh 14 14 pmadrh pmadrl 7 6 0 7 5 4 0 program memory write latches 14 14 14 5 10 pmadrh<6:0> :pmadrl<7:5> flash program memory row row address decode addr write latch #30 1eh write latch #1 01h write latch #0 00h addr addr addr 000h 001fh 001eh 0000h 0001h 001h 003fh 003eh 0020h 0021h 002h 005fh 005eh 0040h 0041h 3feh 7fdfh 7fdeh 7fc0h 7fc1h 3ffh 7fffh 7ffeh 7fe0h 7fe1h 14 r9 r8 r7 r6 r5 r4 r3 - r1 r0 c4 c3 c2 c1 c0 r2 pmadrl<4:0> 400h 8009h - 801fh 8000h - 8003h configuration words user id 0 - 3 8007h C 8008h 8006h devid revid reserved 8004h - 8005h reserved configuration memory cfgs = 0 cfgs = 1 - - downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 103 pic16(l)f1526/7 figure 11-6: flash program memory write flowchart disable interrupts (gie = 0 ) start write operation select program or config. memory (cfgs) select row address (pmadrh:pmadrl) select write operation (free = 0 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end erase operation no delay when writing to program memory latches determine number of words to be written into program or configuration memory. the number of words cannot exceed the number of words per row. (word_cnt) load the value to write (pmdath:pmdatl) update the word counter (word_cnt--) last word to write ? increment address (pmadrh:pmadrl++) unlock sequence (figure x-x) cpu stalls while write operation completes (2ms typical) load write latches only (lwlo = 1 ) write latches to flash (lwlo = 0 ) no yes figure 11-3 figure 11-3 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 104 ? 2011-2015 microchip technology inc. example 11-3: writing to flash program memory ; this write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) ; bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrh ; bank 3 movf addrh,w ; load initial address movwf pmadrh ; movf addrl,w ; movwf pmadrl ; movlw low data_addr ; load initial data address movwf fsr0l ; movlw high data_addr ; load initial data address movwf fsr0h ; bcf pmcon1,cfgs ; not configuration space bsf pmcon1,wren ; enable writes bsf pmcon1,lwlo ; only load write latches loop moviw fsr0++ ; load first data byte into lower movwf pmdatl ; moviw fsr0++ ; load second data byte into upper movwf pmdath ; movf pmadrl,w ; check if lower bits of address are '00000' xorlw 0x1f ; check if we're on the last of 32 addresses andlw 0x1f ; btfsc status,z ; exit if last of 32 words, goto start_write ; movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor ; loads program memory write latches nop ; incf pmadrl,f ; still loading latches increment address goto loop ; write next latches start_write bcf pmcon1,lwlo ; no more loading latches - actually start flash program ; memory write movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor writes ; all the program memory write latches simultaneously nop ; to program memory. ; after nops, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence required sequence downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 105 pic16(l)f1526/7 11.3 modifying flash program memory when modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a ram image. program memory is modified using the following steps: 1. load the starting address of the row to be modified. 2. read the existing data from the row into a ram image. 3. modify the ram image to contain the new data to be written into program memory. 4. load the starting address of the row to be rewritten. 5. erase the program memory row. 6. load the write latches with data from the ram image. 7. initiate a programming operation. figure 11-7: flash program memory modify flowchart start modify operation read operation (figure x.x) erase operation (figure x.x) modify image the words to be modified are changed in the ram image end modify operation write operation use ram image (figure x.x) an image of the entire row read must be stored in ram figure 11-2 figure 11-4 figure 11-5 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 106 ? 2011-2015 microchip technology inc. 11.4 user id, device id and configuration word access instead of accessing program memory, the user ids, device id/revision id and configuration words can be accessed when cfgs = 1 in the pmcon1 register. this is the region that would be pointed to by pc<15> = 1 , but not all addresses are accessible. different access may exist for reads and writes. refer to table 11-2 . when read access is initiated on an address outside the parameters listed in ta b l e 11 - 2 , the pmdath:pmdatl register pair is cleared, reading back 0 s. table 11-2: user id, device id and configuration word access (cfgs = 1 ) example 11-4: configuration word and device id access address function read access write access 8000h-8003h user ids yes yes 8006h device id/revision id yes no 8007h-8008h configuration words 1 and 2 yes no * this code block will read 1 word of program memory at the memory address: * prog_addr_lo (must be 00h-08h) data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select correct bank movlw prog_addr_lo ; movwf pmadrl ; store lsb of address clrf pmadrh ; clear msb of address bsf pmcon1,cfgs ; select configuration space bcf intcon,gie ; disable interrupts bsf pmcon1,rd ; initiate read nop ; executed (see figure 11-2 ) nop ; ignored (see figure 11-2 ) bsf intcon,gie ; restore interrupts movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 107 pic16(l)f1526/7 11.5 write verify it is considered good programming practice to verify that program memory writes agree with the intended value. since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in ram after the last write is complete. figure 11-8: flash program memory verify flowchart start verify operation read operation (figure x.x) end verify operation this routine assumes that the last row of data written was from an image saved in ram. this image will be used to verify the data currently stored in flash program memory. pmdat = ram image ? last word ? fail verify operation no yes yes no figure 11-2 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 108 ? 2011-2015 microchip technology inc. 11.6 register definitions: flash program memory control register 11-1: pmdatl: program memory data low byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pmdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 pmdat<7:0> : read/write value for least significant bits of program memory register 11-2: pmdath: program memory data high byte register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pmdat<13:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 pmdat<13:8> : read/write value for most significant bits of program memory register 11-3: pmadrl: program memory address low byte register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 pmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 pmadr<7:0> : specifies the least significant bits for program memory address register 11-4: pmadrh: program memory address high byte register u-1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 (1) pmadr<14:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 1 bit 6-0 pmadr<14:8> : specifies the most significant bits for program memory address note 1: unimplemented, read as 1 . downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 109 pic16(l)f1526/7 register 11-5: pmcon1: progra m memory control 1 register u-1 r/w-0/0 r/w-0/0 r/w/hc-0/0 r/w/hc-x/q (2) r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 (1) cfgs lwlo free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cl eared hc = bit is cleared by hardware bit 7 unimplemented: read as 1 bit 6 cfgs: configuration select bit 1 = access configuration, user id and device id registers 0 = access flash program memory bit 5 lwlo: load write latches only bit (3) 1 = only the addressed program memory write latch is loaded/updated on the next wr command 0 = the addressed program memory write latch is loaded/ updated and a write of all program memory write latches will be initiated on the next wr command bit 4 free: program flash erase enable bit 1 = performs an erase operation on the next wr command (hardware cleared upon completion) 0 = performs an write operation on the next wr command bit 3 wrerr: program/erase error flag bit 1 = condition indicates an improper program or erase sequenc e attempt or termination (bit is set automatically on any set attempt (write 1 ) of the wr bit). 0 = the program or erase operation completed normally. bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash bit 1 wr: write control bit 1 = initiates a program flash program/erase operation. the operation is self-timed and the bit is cl eared by hardware once operation is complete. the wr bit can only be set (not cleared) in software. 0 = program/erase operation to the flash is complete and inactive. bit 0 rd: read control bit 1 = initiates a program flash read. read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a program flash read. note 1: unimplemented bit, read as 1 . 2: the wrerr bit is automatically set by hardware when a program memory writ e or erase operation is started (wr = 1 ). 3: the lwlo bit is ignored during a progr am memory erase operation (free = 1 ). downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 110 ? 2011-2015 microchip technology inc. table 11-3: summary of registers as sociated with flash program memory table 11-4: summary of configuration word with flash program memory register 11-6: pmcon2: progra m memory control 2 register w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 program memory control register 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 flash memory unlock pattern bits to unlock writes, a 55h must be written first, followed by an aah, before setting the wr bit of the pmcon1 register. the value written to this register is used to unlock the writes. there are specific timing requirements on these writes. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page pmcon1 (1) cfgs lwlo free wrerr wren wr rd 109 pmcon2 program memory control register 2 110 pmadrl pmadrl<7:0> 108 pmadrh (1) pmadrh<6:0> 108 pmdatl pmdatl<7:0> 108 pmdath pmdath<5:0> 108 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 legend: ? = unimplemented location, read as 0 . shaded cells are not used by flash program memory. note 1: unimplemented, read as 1 . name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 fcmen ieso clkouten boren<1:0> 43 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> config2 13:8 lvp debug l pbor borv stvren 45 7:0 vcapen (1) w r t < 1 : 0 > legend: = unimplemented location, read as 0 . shaded cells are not used by flash program memory. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 111 pic16(l)f1526/7 12.0 i/o ports in general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. however, the pin can still be read. each port has three standard registers for its operation. these registers are: trisx registers (data direction) portx registers (reads the levels on the pins of the device) latx registers (output latch) some ports may have one or more of the following additional registers. these registers are: anselx (analog select) wpux (weak pull-up) the data latch (lata register) is useful for read-modify-write operations on the value that the i/o pins are driving. a write operation to the lata register has the same effect as a write to the corresponding porta register. a read of the lata register reads of the values held in the i/o port latches, while a read of the porta register reads the actual i/o pin value. ports that support analog inputs have an associated anselx register. when an ansel bit is set, the digital input buffer associated with that bit is disabled. disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 12-1 . figure 12-1: gene ric i/o port operation table 12-1: port availability per device device porta portb portcportd porte portf portg pic16(l)f1526 pic16(l)f1527 q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to digital peripherals anselx v dd v ss to analog peripherals downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 112 ? 2011-2015 microchip technology inc. 12.1 alternate pin function the alternate pin function control (apfcon) registers are used to steer specific peripheral input and output functions between different pins. the apfcon registers are shown in register 12-1 . for this device family, the following functions can be moved between different pins. timer3 ccp2 these bits have no effect on the values of any tris register. port and tris overrides will be routed to the correct pin. the unselected pin will be unaffected. 12.2 register definitions: alternate pin function control register 12-1: apfcon: alternate pin function co ntrol register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 t3ckisel ccp2sel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-2 unimplemented: read as 0 bit 1 t3ckisel: timer3 input selection bit 1 = t3cki function is on rb4 0 = t3cki function is on rb5 bit 0 ccp2sel: pin selection bit 1 = ccp2 function is on re7 0 = ccp2 function is on rc1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 113 pic16(l)f1526/7 12.3 porta registers 12.3.1 data register porta is an 8-bit wide, bidirectional port. the corresponding data direction register is trisa ( register 12-3 ). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the porta register ( register 12-2 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (lata). 12.3.2 direction control the trisa register ( register 12-3 ) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read 0 . 12.3.3 analog control the ansela register ( register 12-5 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the ansela bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. example 12-1: initializing porta 12.3.4 porta functions and output priorities each porta pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-2 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown in the priority list note: the ansela bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. table 12-2: porta output priority pin name function priority (1) ra0 ra0 ra1 ra1 ra2 ra2 ra3 ra3 ra4 ra4 ra5 ra5 ra6 clkout osc2ra6 ra7 ra7 note 1: priority listed from highest to lowest. ; this code example illustrates ; initializing the porta register. the ; other ports are initialized in the same ; manner. banksel porta ; clrf porta ;init porta banksel lata ;data latch clrf lata ; banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw b'00111000' ;set ra<5:3> as inputs movwf trisa ;and set ra<2:0> as ;outputs downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 114 ? 2011-2015 microchip technology inc. 12.4 register definitions: porta register 12-2: porta: porta register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 ra<7:0> : porta i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i /o pin values. register 12-3: trisa: porta tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 trisa<7:0>: porta tri-state control bits 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output register 12-4: lata: porta data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 lata<7:0> : porta output latch value bits (1) note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i /o pin values. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 115 pic16(l)f1526/7 table 12-3: summary of regist ers associated with porta table 12-4: summary of conf iguration word with porta register 12-5: ansela: porta analog select register u-0 u-0 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ansa5 ansa3 ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5 ansa5 : analog select between analog or digital function on pins ra5, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 4 unimplemented: read as 0 bit 3-0 ansa<3:0> : analog select between analog or digital function on pins ra<3:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela a n s a 5 ansa3 ansa2 ansa1 ansa0 115 apfcon t3ckisel ccp2sel 112 lata lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 114 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 158 porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 114 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 114 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by porta. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 fcmen ieso clkouten boren<1:0> 45 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: = unimplemented location, read as 0 . shaded cells are not used by porta. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 116 ? 2011-2015 microchip technology inc. 12.5 portb registers 12.5.1 data register portb is an 8-bit wide, bidirectional port. the corresponding data direction register is trisb ( register 12-7 ). setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the portb register ( register 12-6 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latb). 12.5.2 direction control the trisb register ( register 12-7 ) controls the portb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read 0 . 12.5.3 analog control the anselb register ( register 12-9 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselb bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the anselb bits has no effect on digital output functions. a pin with tris clear and anselb set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 12.5.4 portb functions and output priorities each portb pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-5 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in tab le 1 2- 5 . note: the anselb bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. table 12-5: portb output priority pin name function priority (1) rb0 rb0 rb1 rb1 rb2 rb2 rb3 ccp2 rb3 rb4 rb4 rb5 rb5 rb6 icdclk rb6 rb7 icddat rb7 note 1: priority listed from highest to lowest. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 117 pic16(l)f1526/7 12.6 register definitions: portb register 12-6: port b: portb register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 rb<7:0> : portb i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portb are actually written to corresponding latb register. reads from portb register is return of actual i/o pin values. register 12-7: trisb: po rtb tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 trisb<7:0>: portb tri-state control bits 1 = portb pin configured as an input (tri-stated) 0 = portb pin configured as an output register 12-8: latb: portb data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 latb<7:0> : portb output latch value bits (1) note 1: writes to portb are actually written to corresponding latb register. reads from portb register is return of actual i/o pin values. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 118 ? 2011-2015 microchip technology inc. table 12-6: summary of regist ers associated with portb register 12-9: anselb: portb analog select register u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 ansb<5:0> : analog select between analog or digital function on pins rb<5:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. register 12-10: wpub: weak pull-up portb register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 wpub<7:0> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon t3ckisel ccp2sel 118 anselb ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 118 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 117 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 117 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 117 wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 118 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0 . shaded cells are not used by portb. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 119 pic16(l)f1526/7 12.7 portc registers 12.7.1 data register portc is an 8-bit wide, bidirectional port. the corresponding data direction register is trisc ( register 12-12 ). setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the portc register ( register 12-11 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latc). 12.7.2 direction control the trisc register ( register 12-12 ) controls the portc pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog input always read 0 . 12.7.3 portc functions and output priorities each portc pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-7 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in the priority list. table 12-7: portc output priority pin name function priority (1) rc0 sosco rc0 rc1 sosci ccp2rc1 rc2 ccp1 rc2 rc3 scl1 sck1rc3 (2) rc4 sda1 rc4 (2) rc5 sdo1 rc5 rc6 ck1 tx1 rc6 rc7 dt1 rc7 note 1: priority listed from highest to lowest. 2: rc3 and rc4 read the i 2 c st input when i 2 c mode is enabled. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 120 ? 2011-2015 microchip technology inc. 12.8 register definitions: portc register 12-11: portc: portc register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 rc<7:0> : portc general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portc are actually written to corresponding latc register. reads from portc register is return of actual i/o pin values. register 12-12: trisc: po rtc tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 trisc<7:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output register 12-13: latc: portc data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 latc<7:0> : portc output latch value bits (1) note 1: writes to portc are actually written to corresponding latc register. reads from portc register is return of actual i/o pin values. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 121 pic16(l)f1526/7 table 12-8: summary of regist ers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon t3ckisel ccp2sel 118 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 117 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 117 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0 . shaded cells are not used by portc. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 122 ? 2011-2015 microchip technology inc. 12.9 portd registers 12.9.1 data register portd is an 8-bit wide, bidirectional port. the corresponding data direction register is trisd ( register 12-15 ). setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the portd register ( register 12-14 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latd). 12.9.2 direction control the trisd register ( register 12-15 ) controls the portd pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisd register are maintained set when using them as analog inputs. i/o pins configured as analog input always read 0 . 12.9.3 analog control the anseld register ( register 12-17 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anseld bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the anseld bits has no effect on digital out- put functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when exe- cuting read-modify-write instructions on the affected port. 12.9.4 portd functions and output priorities each portd pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-9 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in the priority list. note: the anseld bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. table 12-9: portd output priority pin name function priority (1) rd0 rd0 rd1 rd1 rd2 rd2 rd3 rd3 rd4 sdo2 rd4 rd5 sda2 rd5 (2) rd6 scl2 sck2rd6 (2) rd7 rd7 note 1: priority listed from highest to lowest. 2: rd5 and rd6 read the i 2 c st input when i 2 c mode is enabled. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 123 pic16(l)f1526/7 12.10 register definitions: portd register 12-14: portd: portd register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 rd<7:0> : portd general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portd are actually written to corresponding latd register. reads from portd register is return of actual i/o pin values. register 12-15: trisd: po rtd tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 trisd<7:0>: portd tri-state control bits 1 = portd pin configured as an input (tri-stated) 0 = portd pin configured as an output register 12-16: latd: portd data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 latd<7:0> : portd output latch value bits (1) note 1: writes to portd are actually written to corresponding latd register. reads from portd register is return of actual i/o pin values. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 124 ? 2011-2015 microchip technology inc. table 12-10: summary of registers associated with portd register 12-17: anseld: portd analog select register u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ansd3 ansd2 ansd1 ansd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented : read as 0 bit 3-0 ansd<3:0> : analog select between analog or digital function on pins rd<3:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. register 12-18: wpud: weak pull-up portd register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpud7 wpud6 wpud5 wpud4 wpud3 wpud2 wpud1 wpud0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 wpud<7:0> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anseld ansd3 ansd2 ansd1 ansd0 118 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 117 portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 117 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 123 wpud wpud7 wpud6 wpud5 wpud4 wpud3 wpud2 wpud1 wpud0 124 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0 . shaded cells are not used by portd. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 125 pic16(l)f1526/7 12.11 porte registers 12.11.1 data register porte is an 8-bit wide, bidirectional port. the corresponding data direction register is trise ( register 12-20 ). setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the porte register ( register 12-19 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (late). 12.11.2 direction control the trise register ( register 12-20 ) controls the porte pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trise register are maintained set when using them as analog inputs. i/o pins configured as analog input always read 0 . 12.11.3 analog control the ansele register ( register 12-22 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansele bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the ansele bits has no effect on digital output functions. a pin with tris clear and ansele set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 12.11.4 porte functions and output priorities each porte pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-11 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in the priority list. note: the ansele bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. table 12-11: porte output priority pin name function priority (1) re0 re0 re1 re1 re2 ccp10 re2 re3 ccp9 re3 re4 ccp8 re4 re5 ccp7 re5 re6 ccp6 re6 re7 ccp2 re7 note 1: priority listed from highest to lowest. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 126 ? 2011-2015 microchip technology inc. 12.12 register definitions: porte register 12-19: porte: porte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u re7 re6 re5 re4 re3 re2 re1 re0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 re<7:0> : porte general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porte are actually written to corresponding late register. reads from porte register is return of actual i/o pin values. register 12-20: trise: porte tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 trise<7:0>: porte tri-state control bits 1 = porte pin configured as an input (tri-stated) 0 = porte pin configured as an output register 12-21: late: porte data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u late7 late6 late5 late4 late3 late2 late1 late0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 late<7:0> : porte output latch value bits (1) note 1: writes to porte are actually written to corresponding late register. reads from porte register is return of actual i/o pin values. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 127 pic16(l)f1526/7 table 12-12: summary of regist ers associated with porte register 12-22: ansele: po rte analog select register u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 anse2 anse1 anse0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-3 unimplemented : read as 0 bit 2-0 anse<2:0> : analog select between analog or digital function on pins re<2:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. register 12-23: wpue: weak pull-up porte register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpue7 wpue6 wpue5 wpue4 wpue3 wpue2 wpue1 wpue0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 wpue<7:0> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon t3ckisel ccp2sel 118 ansele anse2 anse1 anse0 127 late late7 late6 late5 late4 late3 late2 late1 late0 126 porte re7 re6 re5 re4 re3 re2 re1 re0 126 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 126 wpue wpue7 wpue6 wpue5 wpue4 wpue3 wpue2 wpue1 wpue0 127 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0 . shaded cells are not used by porte. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 128 ? 2011-2015 microchip technology inc. 12.13 portf registers 12.13.1 data register portf is an 8-bit wide, bidirectional port. the corresponding data direction register is trisf ( register 12-25 ). setting a trisf bit (= 1 ) will make the corresponding portf pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisf bit (= 0 ) will make the corresponding portf pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the portf register ( register 12-24 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latf). 12.13.2 direction control the trisf register ( register 12-25 ) controls the portf pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisf register are maintained set when using them as analog inputs. i/o pins configured as analog input always read 0 . 12.13.3 analog control the anself register ( register 12-27 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anself bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the anself bits has no effect on digital output functions. a pin with tris clear and anself set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 12.13.4 porte functions and output priorities each portf pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-13 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in the priority list. note: the anself bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. table 12-13: portf output priority pin name function priority (1) rf0 v cap (2) rf0 rf1 rf1 rf2 rf2 rf3 rf3 rf4 rf4 rf5 rf5 rf6 rf6 rf7 rf7 note 1: priority listed from highest to lowest. 2: pic16f1526/7 only downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 129 pic16(l)f1526/7 12.14 register definitions: portf register 12-24: portf: portf register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 rf<7:0> : portf general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portf are actually written to corresponding latf register. reads from portf register is return of actual i/o pin values. register 12-25: trisf: portf tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 trisf<7:0>: portf tri-state control bits 1 = portf pin configured as an input (tri-stated) 0 = portf pin configured as an output register 12-26: latf: portf data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 latf<7:0> : portf output latch value bits (1) note 1: writes to portf are actually written to corresponding latf register. reads from portf register is return of actual i/o pin values. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 130 ? 2011-2015 microchip technology inc. table 12-14: summary of registers associated with portf table 12-15: summary of conf iguration word with portf register 12-27: anself: por tf analog select register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ansf7 ansf6 ansf5 ansf4 ansf3 ansf2 ansf1 ansf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 ansf<7:0> : analog select between analog or digital function on pins rf<7:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anself ansf7 ansf6 ansf5 ansf4 ansf3 ansf2 ansf1 ansf0 130 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 129 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 129 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 129 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0 . shaded cells are not used by portf. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config2 13:8 lvp debug l pbor borv stvren 45 7:0 vcapen (1) wrt<1:0> legend: = unimplemented locations read as 0 . shaded cells are not used by portf. note 1: pic16f1526/7 only. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 131 pic16(l)f1526/7 12.15 portg registers 12.15.1 data register portg is a 6-bit wide, bidirectional port. the corresponding data direction register is trisg ( register 12-29 ). setting a trisg bit (= 1 ) will make the corresponding portg pin an input (i.e., disable the output driver). clearing a trisg bit (= 0 ) will make the corresponding portg pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). the exception is rg5, which is input only and its tris bit will always read as 1 . example 12-1 shows how to initialize an i/o port. reading the portg register ( register 12-28 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latg). 12.15.2 direction control the trisg register ( register 12-29 ) controls the portg pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisg register are maintained set when using them as analog inputs. i/o pins configured as analog input always read 0 . 12.15.3 analog control the anselg register ( register 12-31 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselg bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the anselg bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 12.15.4 portg functions and output priorities each portg pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-16 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority list. note: the anselg bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. table 12-16: portg output priority pin name function priority (1) rg0 ccp3 rg0 rg1 ck2 tx2 rg1 rg2 dt2 rg2 rg3 ccp4 rg3 rg4 ccp5 rg4 rg5 input only pin note 1: priority listed from highest to lowest. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 132 ? 2011-2015 microchip technology inc. 12.16 register definitions: portg register 12-28: portg: portg register u-0 u-0 r-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rg5 rg4 rg3 rg2 rg1 rg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented : read as 0 bit 5-0 rg<5:0> : portg i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portg are actually written to corresponding latg register. reads from portg register is return of actual i/o pin values. register 12-29: trisg: portg tri-state register u-0 u-0 u-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 (1) trisg4 trisg3 trisg2 trisg1 trisg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented : read as 0 bit 5 unimplemented : read as 1 bit 4-0 trisg<4:0>: rg<4:0> tri-state control bits (1) 1 = portg pin configured as an input (tri-stated) 0 = portg pin configured as an output note 1: unimplemented, read as 1 . downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 133 pic16(l)f1526/7 register 12-30: latg: portg data latch register u-0 u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latg4 latg3 latg2 latg1 latg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-5 unimplemented : read as 0 bit 4-0 latg<4:0> : portg output latch value bits (1) note 1: writes to portg are actually written to corresponding latg register. reads from portg register is return of actual i/o pin values. register 12-31: anselg: po rtg analog select register u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 u-0 ansg4 ansg3 ansg2 ansg1 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-5 unimplemented: read as 0 bit 4-1 ansg<4:1> : analog select between analog or digital function on pins rg<4:1>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 0 unimplemented: read as 0 note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 134 ? 2011-2015 microchip technology inc. table 12-17: summary of registers associated with portg table 12-18: summary of conf iguration word with portg register 12-32: wpug: weak pull-up portg register u-0 u-0 r/w-1/1 u-0 u-0 u-0 u-0 u-0 wpug5 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5 wpug5: weak pull-up register bit 1 = pull-up enabled 0 = pull-up disabled bit 4-0 unimplemented: read as 0 note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselg ansg4 ansg3 ansg2 ansg1 133 latg latg4 latg3 latg2 latg1 latg0 133 portg rg5 rg4 rg3 rg2 rg1 rg0 132 trisg (1) trisg4 trisg3 trisg2 trisg1 trisg0 132 wpug w p u g 5 134 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by portg. note 1: unimplemented, read as 1 . name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 fcmen ieso clkouten boren<1:0> 45 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: = unimplemented location, read as 0 . shaded cells are not used by portg. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 135 pic16(l)f1526/7 13.0 interrupt-on-change the portb pins can be configured to operate as interrupt-on-change (ioc) pins. an interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. any individual portb pin, or combination of portb pins, can be configured to generate an interrupt. the interrupt-on-change module has the following features: interrupt-on-change enable (master switch) individual pin configuration rising and falling edge detection individual pin interrupt flags figure 13-1 is a block diagram of the ioc module. 13.1 enabling the module to allow individual portb pins to generate an interrupt, the iocie bit of the intcon register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 13.2 individual pin configuration for each portb pin, a rising edge detector and a falling edge detector are present. to enable a pin to detect a rising edge, the associated iocbpx bit of the iocbp register is set. to enable a pin to detect a falling edge, the associated iocbnx bit of the iocbn register is set. a pin can be configured to detect rising and falling edges simultaneously by setting both the iocbpx bit and the iocbnx bit of the iocbp and iocbn registers, respectively. 13.3 interrupt flags the iocbfx bits located in the iocbf register are status flags that correspond to the interrupt-on-change pins of portb. if an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the iocie bit is set. the iocif bit of the intcon register reflects the status of all iocbfx bits. 13.4 clearing interrupt flags the individual status flags, (iocbfx bits), can be cleared by resetting them to zero. if another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. in order to ensure that no detected edge is lost while clearing flags, only and operations masking out known changed bits should be performed. the following sequence is an example of what should be performed. example 13-1: clearing interrupt flags (porta example) 13.5 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the iocie bit is set. if an edge is detected while in sleep mode, the iocbf register will be updated prior to the first instruction executed out of sleep. movlw 0xff xorwf iocaf, w andwf iocaf, f downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 136 ? 2011-2015 microchip technology inc. figure 13-1: interrupt-on -change block diagram d ck r q d ck r q rbx iocbnx iocbpx q2 d ck s q q4q1 data bus = 0 or 1 write iocbfx iocie to data bus iocbfx edge detect ioc interrupt to cpu core from all other iocbfx individual pin detectors q1 q2 q3 q4 q4q1 q1 q2 q3 q4 q1 q2 q3 q4 q4 q4q1 q4q1 q4q1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 137 pic16(l)f1526/7 13.6 register definitions: interrupt-on-change control register 13-1: iocbp: interrupt-on-c hange portb positive edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocbp7 iocbp6 iocbp5 iocbp4 iocbp3 iocbp2 iocbp1 iocbp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 iocbp<7:0>: interrupt-on-change portb positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. iocbfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin register 13-2: iocbn: interrupt-on-chan ge portb negative edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 iocbn<7:0>: interrupt-on-change portb negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. iocbfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin register 13-3: iocbf: interrupt- on-change portb flag register r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs - bit is set in hardware bit 7-0 iocbf<7:0>: interrupt-on-change portb flag bits 1 = an enabled change was detected on the associated pin. set when iocbpx = 1 and a rising edge was detected on rbx, or when iocbnx = 1 and a falling edge was detected on rbx. 0 = no change was detected, or the user cleared the detected change. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 138 ? 2011-2015 microchip technology inc. table 13-1: summary of registers as sociated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 118 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 iocbp iocbp7 iocbp6 iocbp5 ioc bp4 iocbp3 iocbp2 iocbp1 iocbp0 137 iocbn iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 137 iocbf iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 137 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 117 legend: = unimplemented location, read as 0 . shaded cells are not used by interrupt-on-change. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 139 pic16(l)f1526/7 14.0 fixed voltage reference (fvr) the fixed voltage reference, or fvr, is a stable voltage reference, independent of v dd , with 1.024v, 2.048v or 4.096v selectable output levels. the output of the fvr can be configured to supply a reference voltage to the following: adc input channel adc positive reference the fvr can be enabled by setting the fvren bit of the fvrcon register. 14.1 independent gain amplifiers the output of the fvr supplied to the adc module is routed through two independent programmable gain amplifiers. each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. refer- ence section 16.0 ?analog-to-digital converter (adc) module? for additional information. 14.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. see section 25.0 ?electrical specifications? for the minimum delay requirement. figure 14-1: voltage reference block diagram fvr_buffer1 (to adc module) x1 x2 x4 + - 1.024v fixed reference fvren fvrrdy 2 adfvr<1:0> any peripheral requiring the fixed reference (see table 14-1 ) table 14-1: peripherals requiring the fixed voltage reference (fvr) peripheral conditions description hfintosc fosc<2:0> = 100 and ircf<3:0> = 000x intosc is active and device is not in sleep. bor boren<1:0> = 11 bor always enabled. boren<1:0> = 10 and borfs = 1 bor disabled in sleep mode, bor fast start enabled. boren<1:0> = 01 and borfs = 1 bor under software control, bor fast start enabled. ldo all pic16f1526/7 devices, when vregpm = 1 and not in sleep the device runs off of the low-power regulator when in sleep mode. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 140 ? 2011-2015 microchip technology inc. 14.3 register definitions: fvr control table 14-2: summary of registers associated with fixed voltage reference register 14-1: fvrcon: fixed voltage reference control register r/w-0/0 r-q/q r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 fvren fvrrdy (1) tsen tsrng adfvr<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 fvren: fixed voltage reference enable bit 1 = fixed voltage reference is enabled 0 = fixed voltage reference is disabled bit 6 fvrrdy: fixed voltage reference ready flag bit (1) 1 = fixed voltage reference output is ready for use 0 = fixed voltage reference output is not ready or not enabled bit 5 tsen: temperature indicator enable bit 1 = temperature indicator is enabled 0 = temperature indicator is disabled bit 4 tsrng: temperature indicator range selection bit 1 =v out = v dd - 4v t (high range) 0 =v out = v dd - 2v t (low range) bit 3-2 unimplemented: read as 0 bit 1-0 adfvr<1:0>: adc fixed voltage reference selection bits 11 = adc fixed voltage reference peripheral output is 4x (4.096v) (2) 10 = adc fixed voltage reference peripheral output is 2x (2.048v) (2) 01 = adc fixed voltage reference peripheral output is 1x (1.024v) 00 = adc fixed voltage reference peripheral output is off note 1: fvrrdy is always 1 on pic16f1526/7 only. 2: fixed voltage reference output cannot exceed v dd . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng a d f v r < 1 : 0 > 140 legend: shaded cells are unused by the fixed voltage reference. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 141 pic16(l)f1526/7 15.0 temperature indicator module this family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuits range of operating temperature falls between -40c and +85c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. the circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. a one-point calibration allows the circuit to indicate a temperature closely surrounding that point. a two-point calibration allows the circuit to sense the entire range of temperature more accurately. reference application note an1333, use and calibration of the internal temperature indicator (ds01333) for more details regarding the calibration process. 15.1 circuit operation figure 15-1 shows a simplified block diagram of the temperature circuit. the proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. equation 15-1 describes the output characteristics of the temperature indicator. equation 15-1: v out ranges the temperature sense circuit is integrated with the fixed voltage reference (fvr) module. see section 14.0 ?fixed voltage reference (fvr)? for more information. the circuit is enabled by setting the tsen bit of the fvrcon register. when disabled, the circuit draws no current. the circuit operates in either high or low range. the high range, selected by setting the tsrng bit of the fvrcon register, provides a wider output voltage. this provides more resolution over the temperature range, but may be less consistent from part to part. this range requires a higher bias voltage to operate and thus, a higher v dd is needed. the low range is selected by clearing the tsrng bit of the fvrcon register. the low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. the low range is provided for low voltage operation. figure 15-1: temperature circuit diagram 15.2 minimum operating v dd when the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. when the temperature circuit is operated in high range, the device operating voltage, v dd , must be high enough to ensure that the temperature circuit is cor- rectly biased. table 15-1 shows the recommended minimum v dd vs. range setting. table 15-1: recommended v dd vs. range 15.3 temperature output the output of the circuit is measured using the internal analog-to-digital converter. a channel is reserved for the temperature circuit output. refer to section 16.0 ?analog-to-digital converter (adc) module? for detailed information. high range: v out = v dd - 4v t low range: v out = v dd - 2v t min. v dd , tsrng = 1 min. v dd , tsrng = 0 3.6v 1.8v note: every time the adc mux is changed to the temperature indicator output selection (chs bit in the adccon0 register), wait 500 ? sec for the sampling capacitor to fully charge before sampling the temperature indicator output. tsen tsrng v dd v out to a d c downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 142 ? 2011-2015 microchip technology inc. 15.4 adc acquisition time to ensure accurate temperature measurements, the user must wait at least 200 ? s after the adc input multiplexer is connected to the temperature indicator output before the conversion is performed. in addition, the user must wait 200 ? s between sequential conversions of the temperature indicator output. table 15-2: summary of registers associated with the temperature indicator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng adfvr<1:0> 140 legend: shaded cells are unused by the temperature indicator module. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 143 pic16(l)f1526/7 16.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresh:adresl register pair). figure 16-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 16-1: adc block diagram note 1: when adon = 0 , all multiplexer inputs are disconnected. 2: see adcon0 register ( example 16-1 ) for detailed analog channel selection per device. temp indicator av dd v ref adpref = 10 adpref = 00 adpref = 11 fvr buffer1 adon (1) go/done av ss adc 0000000001 00010 00011 11110 chs<4:0> (2) an0 an1 an2 v ref +/an3 11111 adresh adresl 10 16 adfm 0 = left justify 1 = right justify an29 11101 0010000101 00110 an4 an5 an6 ref+ downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 144 ? 2011-2015 microchip technology inc. 16.1 adc configuration when configuring and using the adc the following functions must be considered: port configuration channel selection adc voltage reference selection adc conversion clock source interrupt control result formatting 16.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 12.0 ?i/o ports? for more information. 16.1.2 channel selection there are 32 channel selections available: an<29:0> pins temperature indicator fvr (fixed voltage reference) output refer to section 14.0 ?fixed voltage reference (fvr)? and section 15.0 ?temperature indicator module? for more information on these channel selections. the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 16.2 ?adc operation? for more information. 16.1.3 adc voltage reference the adpref bits of the adcon1 register provides control of the positive voltage reference. the positive voltage reference can be: v ref + pin v dd fvr 2.048v fvr 4.096v (not available on lf devices) see section 14.0 ?fixed voltage reference (fvr)? for more details on the fixed voltage reference. 16.1.4 conversion clock the source of the conversion clock is software selectable via the adcs bits of the adcon1 register. there are seven possible clock options: f osc /2 f osc /4 f osc /8 f osc /16 f osc /32 f osc /64 f rc (dedicated internal f rc oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad periods as shown in figure 16-2 . for correct conversion, the appropriate t ad specification must be met. refer to the adc conversion requirements in section 25.0 ?electrical specifications? for more information. table 16-1 gives examples of appropriate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buf- fer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 145 pic16(l)f1526/7 table 16-1: adc clock period (t ad ) v s . device operating frequencies figure 16-2: analog-to-dig ital conversion t ad cycles adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz f osc /2 000 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s f osc /4 100 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4 . 0 ? s f osc /8 001 400 ns (2) 0.5 ? s (2) 1.0 ? s2 . 0 ? s 8.0 ? s (3) f osc /16 101 800 ns 1.0 ? s2 . 0 ? s4 . 0 ? s 16.0 ? s (3) f osc /32 010 1.6 ? s2 . 0 ? s4 . 0 ? s 8.0 ? s (3) 32.0 ? s (3) f osc /64 110 3.2 ? s4 . 0 ? s 8.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 1.6 ? s for v dd . 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: the adc clock period (t ad ) and total adc conversion time can be minimized when the adc clock is derived from the system clock f osc . however, the f rc clock source must be used when conv ersions are to be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 146 ? 2011-2015 microchip technology inc. 16.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruc- tion is always executed. if the user is attempting to wake-up from sleep and resume in-line code execu- tion, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. 16.1.6 result formatting the 10-bit adc conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon1 register controls the output format. figure 16-3 shows the two output formats. figure 16-3: 10-bit adc conv ersion result format note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the f rc oscillator is selected. adresh adresl (adfm = 0 )m s b l s b bit 7 bit 0 bit 7 bit 0 10-bit adc result unimplemented: read as 0 (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as 0 10-bit adc result downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 147 pic16(l)f1526/7 16.2 adc operation 16.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a 1 . setting the go/done bit of the adcon0 register to a 1 will start the analog-to-digital conversion. 16.2.2 completion of a conversion when the conversion is complete, the adc module will: clear the go/done bit set the adif interrupt flag bit update the adresh and adresl registers with new conversion result 16.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh and adresl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 16.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc oscillator source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conver- sion to be aborted and the adc module is turned off, although the adon bit remains set. 16.2.5 special event trigger the special event trigger of the ccpx module allows periodic adc measurements without software intervention. when this trigger occurs, the go/done bit is set by hardware and the timer1 counter resets to zero. using the special event trigger does not assure proper adc timing. it is the users responsibility to ensure that the adc timing requirements are met. refer to section 20.0 ?capture/compare/pwm modules? for more information. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 16.2.6 ?adc conver- sion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. table 16-2: special event trigger device ccp pic16(l)f1526/7 ccp10 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 148 ? 2011-2015 microchip technology inc. 16.2.6 adc conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: disable pin output driver (refer to the tris register) configure pin as analog (refer to the ansel register) disable weak pull-ups either globally (refer to the option_reg register) or individually (refer to the appropriate wpux register) 2. configure the adc module: select adc conversion clock configure voltage reference select adc input channel turn on adc module 3. configure adc interrupt (optional): clear adc interrupt flag enable adc interrupt enable peripheral interrupt enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: polling the go/done bit waiting for the adc interrupt (interrupts enabled) 7. read adc result. 8. clear the adc interrupt flag (required if interrupt is enabled). example 16-1: adc conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 16.4 ?adc acquisition requirements? . ;this code block configures the adc;for polling, v dd and v ss references, frc ;clock and an0 input.; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b11110000 ;right justify, frc ;clock movwf adcon1 ;vdd and vss vref banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel wpua bcf wpua,0 ;disable weak pull-up on ra0 banksel adcon0 ; movlw b00000001 ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,adgo ;start conversion btfsc adcon0,adgo ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 149 pic16(l)f1526/7 16.3 register definitions: adc control register 16-1: adcon0: ad c control register 0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6-2 chs<4:0>: analog channel select bits 11111 = fvr (fixed voltage reference) buffer 1 output (1) 11110 = temperature indicator (2) . 11101 =an29 00110 =an6 00101 =an5 00100 =an4 00011 =an3 00010 =an2 00001 =an1 00000 =an0 bit 1 go/done : adc conversion status bit 1 = adc conversion cycle in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc conversion has completed. 0 = adc conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 14.0 ?fixed voltage reference (fvr)? for more information. 2: see section 15.0 ?temperature indicator module? for more information. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 150 ? 2011-2015 microchip technology inc. register 16-2: adcon1: ad c control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 adfm: adc result format select bit 1 = right justified. six most significant bits of adresh are set to 0 when the conversion result is loaded. 0 = left justified. six least significant bits of adresl are set to 0 when the conversion result is loaded. bit 6-4 adcs<2:0>: adc conversion clock select bits 111 =f rc (clock supplied from a dedicated f rc oscillator) 110 =f osc /64 101 =f osc /16 100 =f osc /4 011 =f rc (clock supplied from a dedicated f rc oscillator) 010 =f osc /32 001 =f osc /8 000 =f osc /2 bit 3-2 unimplemented: read as 0 bit 1-0 adpref<1:0>: adc positive voltage reference configuration bits 11 =v ref + is connected to internal fixed voltage reference (fvr) module (1) 10 =v ref + is connected to external v ref + pin (1) 01 = reserved 00 =v ref + is connected to v dd note 1: when selecting the fvr or the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 25.0 ?electrical specifications? for details. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 151 pic16(l)f1526/7 register 16-3: adresh: adc result register high (adresh) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 adres<9:2> : adc result register bits upper 8 bits of 10-bit conversion result register 16-4: adresl: adc result register low (adresl) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 adres<1:0> : adc result register bits lower 2 bits of 10-bit conversion result bit 5-0 reserved : do not use. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 152 ? 2011-2015 microchip technology inc. register 16-5: adresh: adc result register high (adresh) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper 2 bits of 10-bit conversion result register 16-6: adresl: adc result register low (adresl) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 adres<7:0> : adc result register bits lower 8 bits of 10-bit conversion result downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 153 pic16(l)f1526/7 16.4 adc acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 16-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 16-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an adc acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 16-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 16-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/2047) ? = 10pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.000488) = 1.37 = s v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2s 1.37s 50c- 25c ?? 0.05 s/c ?? ?? ++ = 4.62s = note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 154 ? 2011-2015 microchip technology inc. figure 16-4: analog input model figure 16-5: adc transfer function c pin va rs analog 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf v ss /v ref - 6v sampling switch 5v4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to section 25.0 ?electrical specifications? . r ss = resistance of sampling switch input pin 3ffh 3feh adc output code 3fdh 3fch 03h02h 01h 00h full-scale 3fbh 0.5 lsb v ref - zero-scale transition v ref + transition 1.5 lsb full-scale range analog input voltage downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 155 pic16(l)f1526/7 table 16-3: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 chs<4:0> go/done adon 149 adcon1 adfm adcs<2:0> adpref<1:0> 150 adresh adc result register high 151, 152 adresl adc result register low 151, 152 ansela a n s a 5 ansa3 ansa2 ansa1 ansa0 115 anselb ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 118 anseld ansd3 ansd2 ansd1 ansd0 124 ansele anse2 anse1 anse0 127 anself ansf7 ansf6 ansf5 ansf4 ansf3 ansf2 ansf1 ansf0 130 anselg ansg4 ansg3 ansg2 ansg1 133 ccp1con dc1b<1:0> ccp1m<3:0> 189 ccp2con dc2b<1:0> ccp2m<3:0> 189 ccp3con dc3b<1:0> ccp3m<3:0> 189 ccp4con dc4b<1:0> ccp4m<3:0> 189 ccp5con dc5b<1:0> ccp5m<3:0> 189 ccp6con dc6b<1:0> ccp6m<3:0> 189 ccp7con dc7b<1:0> ccp7m<3:0> 189 ccp8con dc8b<1:0> ccp8m<3:0> 189 ccp9con dc9b<1:0> ccp9m<3:0> 189 ccp10con dc10b<1:0> ccp10m<3:0> 189 fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 140 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 114 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 117 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 123 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 126 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 129 trisg (1) trisg4 trisg3 trisg2 trisg1 trisg0 132 legend: = unimplemented read as 0 . shaded cells are not used for adc module. note 1: unimplemented, read as 1 . downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 156 ? 2011-2015 microchip technology inc. 17.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: 8-bit timer/counter register (tmr0) 8-bit prescaler (independent of watchdog timer) programmable internal or external clock source programmable external clock edge selection interrupt on overflow tmr0 can be used to gate timer1/3/5 figure 17-1 is a block diagram of the timer0 module. 17.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 17.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmr0cs bit of the option_reg register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 17.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on either the rising or falling edge of the t0cki pin. the 8-bit counter mode using the t0cki pin is selected by setting the tmr0cs bit in the option_reg register to 1 . the rising or falling transition of the incrementing edge for either input source is determined by the tmr0se bit in the option_reg register. figure 17-1: block diagra m of the timer0 note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. t0cki tmr0se tmr0 ps<2:0> data bus set flag bit tmr0if on overflow tmr0cs 01 0 1 8 8 8-bit prescaler f osc /4 psa sync 2 t cy overflow to timer1/3/5 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 157 pic16(l)f1526/7 17.1.3 software programmable prescaler a software programmable prescaler is available for exclusive use with timer0. the prescaler is enabled by clearing the psa bit of the option_reg register. there are 8 prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option_reg register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be disabled by setting the psa bit of the option_reg register. the prescaler is not readable or writable. all instructions writing to the tmr0 register will clear the prescaler. 17.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the tmr0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the tmr0if bit can only be cleared in software. the timer0 interrupt enable is the tmr0ie bit of the intcon register. 17.1.5 8-bit counter mode synchronization when in 8-bit counter mode, the incrementing edge on the t0cki pin must be synchronized to the instruction clock. synchronization can be accomplished by sampling the prescaler output on the q2 and q4 cycles of the instruction clock. the high and low periods of the external clocking source must meet the timing requirements as shown in section 25.0 ?electrical specifications? . 17.1.6 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. note: the watchdog timer (wdt) uses its own independent prescaler. note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 158 ? 2011-2015 microchip technology inc. 17.2 register definitions: option register table 17-1: summary of registers associated with timer0 register 17-1: option_reg: option register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpuen intedg tmr0cs tmr0se psa ps<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 wpuen : weak pull-up enable bit 1 = all weak pull-ups are disabled (except mclr , if it is enabled) 0 = weak pull-ups are enabled by individual wpua latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 tmr0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is not assigned to the timer0 module 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 option_reg wpuen intedg tmr0cs tmr0se psa ps < 2:0> 158 tmr0 timer0 module register 156* trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 114 legend: = unimplemented locations, read as 0 . shaded cells are not used by the timer0 module. * page provides register information. 000001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit value timer0 rate downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 159 pic16(l)f1526/7 18.0 timer1/3/5 module with gate control the timer1/3/5 module is a 16-bit timer/counter with the following features: 16-bit timer/counter register pair (tmrxh:tmrxl) programmable internal or external clock source 2-bit prescaler dedicated 32 khz oscillator circuit optionally synchronized comparator out multiple timer1/3/5 gate (count enable) sources interrupt on overflow wake-up on overflow (external clock, asynchronous mode only) time base for the capture/compare function auto-conversion trigger (with ccp) selectable gate source polarity gate toggle mode gate single-pulse mode gate value status gate event interrupt figure 18-1 is a block diagram of the timer1/3/5 module. . figure 18-1: timer1/3/5 block diagram note: the x variable used in this section is used to designate timer1, timer3 or timer5. for example, txcon references t1con, t3con or t5con. prx references pr1, pr3 or pr5. tmrxh tmrxl txsync txckps<1:0> prescaler 1, 2, 4, 8 01 synchronized clock input 2 set flag bit tmrxif on overflow tmrx (2) tmrxon note 1: st buffer is high-speed type when using txcki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep. 4: see table 18-4 for timer selection. txg f osc /4 internal clock tmrxcs<1:0> synchronize (3) det sleep input tmrxge 01 00 01 10 11 txgpol d q ck q 01 txgval txgtm single pulse acq. control txgspm txggo/done txgss<1:0> 10 1100 01 f osc internal clock lfintosc r d en q q1 rd t1gcon data bus det interrupt tmrxgif set txclk f osc /2 internal clock d en q txg_in tmrxon from timer0 timer2/4/6 overflow timer10 overflow overflow (4) to comparator module sosc/txcki secondary oscillator (see figure 18-2 ) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 160 ? 2011-2015 microchip technology inc. figure 18-2: timer1/3/5 cl ock source diagram note 1: st buffer is high-speed type when using txcki. secondary sosco/t1cki sosci t1con[soscen] 01 tmr1cs<1:0> (1) en out 1011 00 01 to clock switching (sosc users) t3con[soscen] t5con[soscen] timer 1 tmr3cs<1:0> 10 timer 3 tmr5cs<1:0> 10 timer 5 10 10 t3cki t5cki (1) (1) oscillator timer1 timer3 timer5 1100 01 1100 01 lfintosc f osc /4 fosc lfintosc f osc /4 fosc lfintosc f osc /4 fosc downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 161 pic16(l)f1526/7 18.1 timer1/3/5 operation the timer1/3/5 module is a 16-bit incrementing counter which is accessed through the tmrxh:tmrxl register pair. writes to tmrxh or tmrxl directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source. timer1/3/5 is enabled by configuring the tmrxon and tmrxge bits in the txcon and txgcon registers, respectively. table 18-1 displays the timer1/3/5 enable selections. 18.2 clock source selection the tmrxcs<1:0> and soscen bits of the txcon register are used to select the clock source for timer1/3/5. table 18-2 displays the clock source selections. 18.2.1 internal clock source when the internal clock source is selected, the tmrxh:tmrxl register pair will increment on multiples of f osc as determined by the timer1/3/5 prescaler. when the f osc internal clock source is selected, the timer1/3/5 register value will increment by four counts every instruction clock cycle. due to this condition, a 2 lsb error in resolution will occur when reading the timer1/3/5 value. to utilize the full resolution of timer1/3/5, an asynchronous input signal must be used to gate the timer1/3/5 clock input. the following asynchronous sources may be used: asynchronous event on the txg pin to timer1/3/5 gate 18.2.2 external clock source when the external clock source is selected, the tim- er1/3/5 module may work as a timer or a counter. when enabled to count, timer1/3/5 is incremented on the rising edge of the external clock input txcki. these external clock inputs (txcki) can be synchronized to the microcontroller system clock or they can run asynchronously. when used as a timer with a clock oscillator, an external 32.768 khz crystal can be used in conjunction with the dedicated internal oscillator circuit. table 18-1: timer1/3/5 enable selections tmrxon tmrxge timer1/3/5 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: timer1/3/5 enabled after por write to tmrxh or tmrxl timer1/3/5 is disabled timer1/3/5 is disabled (tmrxon = 0 ) when txcki is high then timer1/3/5 is enabled (tmrxon = 1 ) when txcki is low. table 18-2: clock source selections tmrxcs<1:0> soscen clock source 00 x instruction clock (f osc /4) 01 x system clock (f osc ) 10 0 external clocking on txcki pin 1 secondary oscillator circuit on sosci/sosco pins 11 x lfintosc downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 162 ? 2011-2015 microchip technology inc. 18.3 timer1/3/5 prescaler timer1/3/5 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the txckps bits of the txcon register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmrxh or tmrxl. 18.4 timer1/3/5 oscillator a dedicated low-power 32.768 khz oscillator circuit is built-in between pins sosci (input) and sosco (amplifier output). this internal circuit is to be used in conjunction with an external 32.768 khz crystal. the oscillator circuit is enabled by setting the soscen bit of the txcon register. the oscillator will continue to run during sleep. 18.5 timer1/3/5 operation in asynchronous counter mode if control bit txsync of the txcon register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if the external clock source is selected then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 18.5.1 ?reading and writing timer1/3/5 in asynchronous counter mode? ). 18.5.1 reading and writing timer1/3/5 in asynchronous counter mode reading tmrxh or tmrxl while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmrxh:tmrxl register pair. 18.6 timer1/3/5 gate timer1/3/5 can be configured to count freely or the count can be enabled and disabled using timer1/3/5 gate circuitry. this is also referred to as timer1/3/5 gate enable. timer1/3/5 gate can also be driven by multiple select- able sources. 18.6.1 timer1/3/5 gate enable the timer1/3/5 gate enable mode is enabled by set- ting the tmrxge bit of the txgcon register. the polarity of the timer1/3/5 gate enable mode is config- ured using the txgpol bit of the txgcon register. when timer1/3/5 gate enable mode is enabled, timer1/3/5 will increment on the rising edge of the timer1/3/5 clock source. when timer1/3/5 gate enable mode is disabled, no incrementing will occur and timer1/3/5 will hold the current count. see figure 18-4 for timing details. note: the oscillator requires a start-up and stabilization time before use. thus, soscen should be set and a suitable delay observed prior to enabling timer1/3/5. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. table 18-3: timer1/3/5 gate enable selections txclk txgpol txg timer1/3/5 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 163 pic16(l)f1526/7 18.6.2 timer1/3/5 gate source selection the timer1/3/5 gate source can be selected from one of four different sources. source selection is controlled by the txgss bits of the txgcon register. the polarity for each available source is also selectable. polarity selection is controlled by the txgpol bit of the txgcon register. table 18-4: timer1/3/5 gate sources 18.6.2.1 txg pin gate operation the txg pin is one source for timer1/3/5 gate control. it can be used to supply an external source to the tim- er1/3/5 gate circuitry. 18.6.2.2 timer0 overflow gate operation when timer0 increments from ffh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the timer1/3/5 gate circuitry. 18.6.3 timer1/3/5 gate toggle mode when timer1/3/5 gate toggle mode is enabled, it is possible to measure the full-cycle length of a tim- er1/3/5 gate signal, as opposed to the duration of a sin- gle level pulse. the timer1/3/5 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. see figure 18-5 for timing details. timer1/3/5 gate toggle mode is enabled by setting the txgtm bit of the txgcon register. when the txgtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 18.6.4 timer1/3/5 gate single-pulse mode when timer1/3/5 gate single-pulse mode is enabled, it is possible to capture a single-pulse gate event. timer1/3/5 gate single-pulse mode is first enabled by setting the txgspm bit in the txgcon register. next, the txggo/done bit in the txgcon register must be set. the timer1/3/5 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the txggo/done bit will automatically be cleared. no other gate events will be allowed to increment timer1/3/5 until the txggo/done bit is once again set in software. see figure 18-6 for timing details. if the single-pulse gate mode is disabled by clearing the txgspm bit in the txgcon register, the txggo/done bit should also be cleared. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1/3/5 gate source to be measured. see figure 18-7 for timing details. 18.6.5 timer1/3/5 gate value status when timer1/3/5 gate value status is utilized, it is pos- sible to read the most current level of the gate control value. the value is stored in the txgval bit in the txgcon register. the txgval bit is valid even when the timer1/3/5 gate is not enabled (tmrxge bit is cleared). t1gss timer1 gate source timer3 gate source timer5 gate source 00 t1g pin t3g pin t5g pin 01 overflow of timer0 (tmr0 increments from ffh to 00h) 10 timer2 match pr2 (tmr2 increments to match pr2) timer4 match pr4 timer6 match pr6 11 timer10 match pr10 note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 164 ? 2011-2015 microchip technology inc. 18.6.6 timer1/3/5 gate event interrupt when timer1/3/5 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. when the falling edge of txgval occurs, the tmrxgif flag bit in the pir1 register will be set. if the tmrxgie bit in the pie1 register is set, then an interrupt will be recognized. the tmrxgif flag bit operates even when the tim- er1/3/5 gate is not enabled (tmrxge bit is cleared). 18.7 timer1/3/5 interrupt the timer1/3/5 register pair (tmrxh:tmrxl) increments to ffffh and rolls over to 0000h. when timer1/3/5 rolls over, the timer1/3/5 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: tmrxon bit of the txcon register tmrxie bit of the pie1 register peie bit of the intcon register gie bit of the intcon register the interrupt is cleared by clearing the tmrxif bit in the interrupt service routine. 18.8 timer1/3/5 operation during sleep timer1/3/5 can only operate during sleep when setup in asynchronous counter mode. in this mode, an exter- nal crystal or clock source can be used to increment the counter. to set up the timer to wake the device: tmrxon bit of the txcon register must be set tmrxie bit of the pie1 register must be set peie bit of the intcon register must be set txsync bit of the txcon register must be set tmrxcs bits of the txcon register must be configured soscen bit of the txcon register must be configured the device will wake-up on an overflow and execute the next instructions. if the gie bit of the intcon register is set, the device will call the interrupt service routine. timer1/3/5 oscillator will continue to operate in sleep regardless of the txsync bit setting. 18.9 eccp/ccp capture/compare time base the ccp module uses the tmrxh:tmrxl register pair as the time base when operating in capture or com- pare mode. in capture mode, the value in the tmrxh:tmrxl register pair is copied into the ccpr1h:ccpr1l register pair on a configured event. in compare mode, an event is triggered when the value ccpr1h:ccpr1l register pair matches the value in the tmrxh:tmrxl register pair. this event can be a special event trigger. for more information, see section 20.0 ?capture/compare/pwm modules? . 18.10 eccp/ccp special event trigger when the ccp is configured to trigger a special event, the trigger will clear the tmrxh:tmrxl register pair. this special event does not cause a timer1/3/5 inter- rupt. the ccp module may still be configured to gener- ate a ccp interrupt. in this mode of operation, the ccpr1h:ccpr1l register pair becomes the period register for timer1/3/5. timer1/3/5 should be synchronized and f osc /4 should be selected as the clock source in order to utilize the special event trigger. asynchronous operation of tim- er1/3/5 can cause a special event trigger to be missed. in the event that a write to tmrxh or tmrxl coincides with a special event trigger from the ccp, the write will take precedence. for more information, see section 16.2.5 ?special event trigger? . note: the tmrxh:tmrxl register pair and the tmrxif bit should be cleared before enabling interrupts. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 165 pic16(l)f1526/7 figure 18-3: timer1/3/5 incrementing edge figure 18-4: timer1/3/5 gate enable mode txcki = 1 when tmr1 enabled txcki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the count er prior to the first incrementing rising edge of the clock. tmrxge txgpol txg_in txcki txgval timer1/3/5 n n + 1 n + 2 n + 3 n + 4 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 166 ? 2011-2015 microchip technology inc. figure 18-5: timer1/3/5 gate toggle mode figure 18-6: timer1/3/5 gate single-pulse mode tmrxge txgpol txgtm txg_in txcki txgval timer1/3/5 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 tmrxge txgpol txg_in txcki txgval timer1/3/5 n n + 1 n + 2 txgspm txggo/ done set by software cleared by hardware on falling edge of txgval set by hardware on falling edge of txgval cleared by software cleared by software tmrxgif counting enabled on rising edge of txg downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 167 pic16(l)f1526/7 figure 18-7: timer1/3/5 gate single -pulse and toggle combined mode tmrxge txgpol txg_in txcki txgval timer1/3/5 nn + 1 n + 2 txgspm txggo/ done set by software cleared by hardware on falling edge of txgval set by hardware on falling edge of txgval cleared by software cleared by software tmrxgif txgtm counting enabled on rising edge of txg n + 4 n + 3 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 168 ? 2011-2015 microchip technology inc. 18.11 register definitions: timer1/3/5 control register 18-1: txcon: time r1/3/5 control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u u-0 r/w-0/u tmrxcs<1:0> txckps<1:0> soscen txsync t m r x o n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 tmrxcs<1:0>: timer1/3/5 clock source select bits 11 = timer1/3/5 clock source is lfintosc 10 = timer1/3/5 clock source is pin or oscillator: if soscen = 0 : external clock from txcki pin (on the rising edge) if soscen = 1 : crystal oscillator on sosci/sosco pins 01 = timer1/3/5 clock source is system clock (f osc ) 00 = timer1/3/5 clock source is instruction clock (f osc /4) bit 5-4 txckps<1:0>: timer1/3/5 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 soscen: lp oscillator enable control bit 1 = dedicated secondary oscillator circuit enabled 0 = dedicated secondary oscillator circuit disabled bit 2 tx sync : timer1/3/5 external clock input synchronization control bit tmrxcs<1:0> = 1x : 1 = do not synchronize external clock input 0 = synchronize external clock input with system clock (f osc ) tmrxcs<1:0> = 0x : this bit is ignored. bit 1 unimplemented: read as 0 bit 0 tmrxon: timer1/3/5 on bit 1 = enables timer1/3/5 0 = stops timer1/3/5 clears timer1/3/5 gate flip-flop downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 169 pic16(l)f1526/7 18.12 register definitions: timer1/3/5 gate control register 18-2: txgcon: timer1/3/5 gate control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w/hc-0/u r-x/x r/w-0/u r/w-0/u tmrxge txgpol txgtm txgspm txggo/ done txgval txgss<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hc = bit is cleared by hardware bit 7 tmrxge: timer1/3/5 gate enable bit if tmrxon = 0 : this bit is ignored if tmrxon = 1 : 1 = timer1/3/5 counting is controlled by the timer1/3/5 gate function 0 = timer1/3/5 counts regardless of timer1/3/5 gate function bit 6 txgpol: timer1/3/5 gate polarity bit 1 = timer1/3/5 gate is active-high (timer1/3/5 counts when gate is high) 0 = timer1/3/5 gate is active-low (timer1/3/5 counts when gate is low) bit 5 txgtm: timer1/3/5 gate toggle mode bit 1 = timer1/3/5 gate toggle mode is enabled 0 = timer1/3/5 gate toggle mode is disabled and toggle flip-flop is cleared timer1/3/5 gate flip-flop toggles on every rising edge. bit 4 txgspm: timer1/3/5 gate single-pulse mode bit 1 = timer1/3/5 gate single-pulse mode is enabled and is controlling timer1/3/5 gate 0 = timer1/3/5 gate single-pulse mode is disabled bit 3 txggo/done : timer1/3/5 gate single-pulse acquisition status bit 1 = timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge 0 = timer1/3/5 gate single-pulse acquisition has completed or has not been started bit 2 txgval: timer1/3/5 gate current state bit indicates the current state of the timer1/3/5 gate that could be provided to tmrxh:tmrxl. unaffected by timer1/3/5 gate enable (tmrxge). bit 1-0 txgss<1:0>: timer1/3/5 gate source select bits 11 = timer10 match pr10 10 = timer2/4/6/8 match pr2/pr4/pr6/pr8 (1) 01 = timer0 overflow output 00 = timer1/3/5 gate pin note 1: see table 18-4 for timer selection. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 170 ? 2011-2015 microchip technology inc. 18.12.1 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 18-5: summary of registers associated with timer1/3/5 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela a n s a 5 ansa3 ansa2 ansa1 ansa0 115 apfcon t3ckisel ccp2sel 112 ccp1con dc1b<1:0> ccp1m<3:0> 189 ccp2con dc2b<1:0> ccp2m<3:0> 189 ccp3con dc3b<1:0> ccp3m<3:0> 189 ccp4con dc4b<1:0> ccp4m<3:0> 189 ccp5con dc5b<1:0> ccp5m<3:0> 189 ccp6con dc6b<1:0> ccp6m<3:0> 189 ccp7con dc7b<1:0> ccp7m<3:0> 189 ccp8con dc8b<1:0> ccp8m<3:0> 189 ccp9con dc9b<1:0> ccp9m<3:0> 189 ccp10con dc10b<1:0> ccp10m<3:0> 189 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 78 pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 79 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 83 tmr1h holding register for the most significant byte of the 16-bit tmr1 register 164* tmr3h holding register for the most significant byte of the 16-bit tmr3 register 164* tmr5h holding register for the most significant byte of the 16-bit tmr5 register 164* tmr1l holding register for the least significant byte of the 16-bit tmr1 register 164* tmr3l holding register for the least significant byte of the 16-bit tmr3 register 164* tmr5l holding register for the least significant byte of the 16-bit tmr5 register 164* trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 114 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync t m r 1 o n 168 t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync t m r 3 o n 168 t5con tmr5cs<1:0> t5ckps<1:0> soscen t5sync t m r 5 o n 168 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 169 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/ done t3gval t3gss<1:0> 169 t5gcon tmr5ge t5gpol t5gtm t5gspm t5ggo/ done t5gval t5gss<1:0> 169 legend: = unimplemented, read as 0 . shaded cells are not used by the timer1/3/5 module. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 171 pic16(l)f1526/7 19.0 timer2/4/6/8/10 modules there are up to five identical timer2-type modules available. to maintain pre-existing naming conventions, the timers are called timer2, timer4, timer6, timer8 and timer10 (also timer2/4/6/8/10). the timer2/4/6/8/10 modules incorporate the following features: 8-bit timer and period registers (tmr2/4/6/8/10 and pr2/4/6/8/10, respectively) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16, and 1:64) software programmable postscaler (1:1 to 1:16) interrupt on tmr2/4/6/8/10 match with pr2/4/6/8/10, respectively optional use as the shift clock for the msspx modules (timer2 only) see figure 19-1 for a block diagram of tim- er2/4/6/8/10. figure 19-1: timer2/4/6/8/10 block diagram note: the x variable used in this section is used to designate timer2, timer4, timer6, timer8 or timer10. for example, txcon references t2con, t4con, t6con, t8con or t10con. prx references pr2, pr4, pr6, pr8 or pr10. comparator tmrx output sets flag bit tmrxif tmrx reset postscaler prescaler prx 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16, 1:64 eq 4 txoutps<3:0> txckps<1:0> downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 172 ? 2011-2015 microchip technology inc. 19.1 timer2/4/6/8/10 operation the clock input to the timer2/4/6/8/10 modules is the system instruction clock (f osc /4). tmr2/4/6/8/10 increments from 00h on each clock edge. a 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. these options are selected by the prescaler control bits, txckps<1:0> of the txcon register. the value of tmr2/4/6/8/10 is compared to that of the period register, pr2/4/6/8/10, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2/4/6/8/10 to 00h on the next cycle and drives the output counter/postscaler (see section 19.2 ?timer2/4/6/8/10 interrupt? ). the tmr2/4/6/8/10 and pr2/4/6/8/10 registers are both directly readable and writable. the tmr2/4/6/8/10 register is cleared on any device reset, whereas the pr2/4/6/8/10 register initializes to ffh. both the prescaler and postscaler counters are cleared on the following events: a write to the tmr2/4/6/8/10 register a write to the txcon register power-on reset (por) brown-out reset (bor) mclr reset watchdog timer (wdt) reset stack overflow reset stack underflow reset reset instruction 19.2 timer2/4/6/8/10 interrupt timer2/4/6/8/10 can also generate an optional device interrupt. the timer2/4/6/8/10 output signal (tmrx-to-prx match) provid es the input for the 4-bit counter/postscaler. this counter generates the tmrx match interrupt flag which is latched in tmrxif of the pirx register. the interrupt is enabled by setting the tmr2/4/6/8/10 match interrupt enable bit, tmrxie of the piex register. a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, txoutps<3:0>, of the txcon register. 19.3 timer2/4/6/8/10 output the unscaled output of tmr2/4/6/8/10 is available pri- marily to the ccp modules, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the msspx modules operating in spi mode. additional information is provided in section 21.1 ?master sspx (msspx) module overview? 19.4 timer2/4/6/8/10 operation during sleep the timer2/4/6/8/10 timers cannot be operated while the processor is in sleep mode. the contents of the tmr2/4/6/8/10 and pr2/4/6/8/10 registers will remain unchanged while the processor is in sleep mode. note: tmr2/4/6/8/10 is not cleared when txcon is written. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 173 pic16(l)f1526/7 19.5 register definitions: timer2/4/6/8/10 control register 19-1: txcon: timer2/timer4/ti mer6/timer8/timer10 control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 txoutps<3:0> tmrxon txckps<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6-3 txoutps<3:0>: timerx output postscaler select bits 1111 = 1:16 postscaler 1110 = 1:15 postscaler 1101 = 1:14 postscaler 1100 = 1:13 postscaler 1011 = 1:12 postscaler 1010 = 1:11 postscaler 1001 = 1:10 postscaler 1000 = 1:9 postscaler 0111 = 1:8 postscaler 0110 = 1:7 postscaler 0101 = 1:6 postscaler 0100 = 1:5 postscaler 0011 = 1:4 postscaler 0010 = 1:3 postscaler 0001 = 1:2 postscaler 0000 =1:1 postscaler bit 2 tmrxon: timerx on bit 1 = timer2/4/6 is on 0 = timer2/4/6 is off bit 1-0 txckps<1:0>: timer2-type clock prescale select bits 11 = prescaler is 64 10 = prescaler is 16 01 =prescaler is 4 00 =prescaler is 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 174 ? 2011-2015 microchip technology inc. table 19-1: summary of registers associated with timer2/4/6/8/10 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ccp1con dc1b<1:0> ccp1m<3:0> 189 ccp2con dc2b<1:0> ccp2m<3:0> 189 ccp3con dc3b<1:0> ccp3m<3:0> 189 ccp4con dc4b<1:0> ccp4m<3:0> 189 ccp5con dc5b<1:0> ccp5m<3:0> 189 ccp6con dc6b<1:0> ccp6m<3:0> 189 ccp7con dc7b<1:0> ccp7m<3:0> 189 ccp8con dc8b<1:0> ccp8m<3:0> 189 ccp9con dc9b<1:0> ccp9m<3:0> 189 ccp10con dc10b<1:0> ccp10m<3:0> 189 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 78 pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 79 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 83 pr2 timer2 module period register 213* pr4 timer4 module period register 213* pr6 timer6 module period register 213* pr8 timer8 module period register 213* pr10 timer10 module period register 213* t2con t2outps<3:0> tmr2on t2ckps1 t2ckps0 215 t4con t4outps<3:0> tmr4on t4ckps1 t4ckps0 215 t6con t6outps<3:0> tmr6on t6ckps1 t6ckps0 215 t8con t8outps<3:0> tmr8on t8ckps1 t8ckps0 215 t10con t10outps<3:0> tmr10on t10ckps1 t10ckps0 215 tmr2 holding register for the 8-bit tmr2 register 213* tmr4 holding register for the 8-bit tmr4 register (1) 213* tmr6 holding register for the 8-bit tmr6 register (1) 213* tmr8 holding register for the 8-bit tmr8 register (1) 213* tmr10 holding register for the 8-bit tmr10 register (1) 213* legend: = unimplemented location, read as 0 . shaded cells are not used for timer2/4/6/8/10 module. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 175 pic16(l)f1526/7 20.0 capture/compare/pwm modules the capture/compare/pwm module is a peripheral which allows the user to time and control different events, and to generate pulse-width modulation (pwm) signals. in capture mode, the peripheral allows the timing of the duration of an event. the compare mode allows the user to trigger an external event when a predetermined amount of time has expired. the pwm mode can generate pulse-width modulated signals of varying frequency and duty cycle. this device contains ten standard capture/compare/pwm modules (ccp1 through ccp10). the capture and compare functions are identical for all ccp modules. note 1: in devices with more than one ccp module, it is very important to pay close attention to the register names used. a number placed after the module acronym is used to distinguish between separate modules. for example, the ccp1con and ccp2con control the same operational aspects of two completely different ccp modules. 2: throughout this section, generic references to a ccp module in any of its operating modes may be interpreted as being equally applicable to any ccpx module. register names, module signals, i/o pins, and bit names may use the generic designator 'x' to indicate the use of a numeral to distinguish a particular module, when required. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 176 ? 2011-2015 microchip technology inc. 20.1 capture mode the capture mode function described in this section is available and identical for ccp modules. capture mode makes use of the 16-bit timer1/3/5 resource. when an event occurs on the ccpx pin, the 16-bit ccprxh:ccprxl register pair captures and stores the 16-bit value of the tmrxh:tmrxl register pair, respectively. an event is defined as one of the following and is configured by the ccpxm<3:0> bits of the ccpxcon register: every falling edge every rising edge every 4th rising edge every 16th rising edge when a capture is made, the interrupt request flag bit ccpxif of the pirx register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in the ccprxh, ccprxl register pair is read, the old captured value is overwritten by the new captured value. figure 20-1 shows a simplified diagram of the capture operation. 20.1.1 ccp pin configuration in capture mode, the ccpx pin should be configured as an input by setting the associated tris control bit. also, the ccp2x pin function can be moved to alternative pins using the apfcon register. refer to section 12.1 ?alternate pin function? for more details. figure 20-1: capture mode operation block diagram 20.1.2 timer1/3/5 mode resource timer1/3/5 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in a synchronous counter mode, the capture operation may not work. see section 18.0 ?timer1/3/5 module with gate control? for more information on configuring timer1/3/5. 20.1.3 software interrupt mode when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccpxie interrupt enable bit of the piex register clear to avoid false interrupts. additionally, the user should clear the ccpxif interrupt flag bit of the pirx register following any change in operating mode. note: if the ccpx pin is configured as an output, a write to the port can cause a capture condition. ccprxh ccprxl tmrxh tmrxl set flag bit ccpxif (pirx register) capture enable ccpxm<3:0> prescaler ? 1, 4, 16 and edge detect pin ccpx system clock (f osc ) table 20-1: ccpx capture timer1/3/5 resources ccp tmr1 tmr3 tmr5 ccp1 ccp2 ccp3 ccp4 ccp5 ccp6 ccp7 ccp8 ccp9 ccp10 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 177 pic16(l)f1526/7 20.1.4 ccp prescaler there are four prescaler settings specified by the ccpxm<3:0> bits of the ccpxcon register. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. to avoid this unexpected operation, turn the module off by clearing the ccpxcon register before changing the prescaler. equation 20-1 demonstrates the code to perform this function. example 20-1: changing between capture prescalers 20.1.5 capture during sleep capture mode depends upon the timer1/3/5 module for proper operation. there are two options for driving the timer1/3/5 module in capture mode. it can be driven by the instruction clock (f osc /4), or by an external clock source. when timer1/3/5 is clocked by f osc /4, timer1/3/5 will not increment during sleep. when the device wakes from sleep, timer1/3/5 will continue from its previous state. capture mode will operate during sleep when tim- er1/3/5 is clocked by an external clock source. 20.1.6 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. banksel ccpxcon ;set bank bits to point ;to ccpxcon clrf ccpxcon ;turn ccp module off movlw new_capt_ps ;load the w reg with ;the new prescaler ;move value and ccp on movwf ccpxcon ;load ccpxcon with this ;value downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 178 ? 2011-2015 microchip technology inc. table 20-2: summary of registers associated with capture name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon t3ckisel ccp2sel 112 ccp1con dc1b<1:0> ccp1m<3:0> 189 ccp2con dc2b<1:0> ccp2m<3:0> 189 ccp3con dc3b<1:0> ccp3m<3:0> 189 ccp4con dc4b<1:0> ccp4m<3:0> 189 ccp5con dc5b<1:0> ccp5m<3:0> 189 ccp6con dc6b<1:0> ccp6m<3:0> 189 ccp7con dc7b<1:0> ccp7m<3:0> 189 ccp8con dc8b<1:0> ccp8m<3:0> 189 ccp9con dc9b<1:0> ccp9m<3:0> 189 ccp10con dc10b<1:0> ccp10m<3:0> 189 ccpr1l capture/compare/pwm register 1 low byte (lsb) 176* ccpr2l capture/compare/pwm register 2 low byte (lsb) 176* ccpr3l capture/compare/pwm register 3 low byte (lsb) 176* ccpr4l capture/compare/pwm register 4 low byte (lsb) 176* ccpr5l capture/compare/pwm register 5 low byte (lsb) 176* ccpr6l capture/compare/pwm register 6 low byte (lsb) 176* ccpr7l capture/compare/pwm register 7 low byte (lsb) 176* ccpr8l capture/compare/pwm register 8 low byte (lsb) 176* ccpr9l capture/compare/pwm register 9 low byte (lsb) 176* ccpr10l capture/compare/pwm register 10 low byte (lsb) 176* ccpr1h capture/compare/pwm register 1 high byte (msb) 176* ccpr2h capture/compare/pwm register 2 high byte (msb) 176* ccpr3h capture/compare/pwm register 3 high byte (msb) 176* ccpr4h capture/compare/pwm register 4 high byte (msb) 176* ccpr5h capture/compare/pwm register 5 high byte (msb) 176* ccpr6h capture/compare/pwm register 6 high byte (msb) 176* ccpr7h capture/compare/pwm register 7 high byte (msb) 176* ccpr8h capture/compare/pwm register 8 high byte (msb) 176* ccpr9h capture/compare/pwm register 9 high byte (msb) 176* ccpr10h capture/compare/pwm register 10 high byte (msb) 176* intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 78 pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 79 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 83 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync tmr1on 168 t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync tmr3on 168 t5con tmr5cs<1:0> t5ckps<1:0> soscen t5sync tmr5on 168 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 169 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/done t3gval t3gss<1:0> 169 legend: = unimplemented location, read as 0 . shaded cells are not used by capture mode. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 179 pic16(l)f1526/7 table 20-2: summary of registers associated with capture (continued) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page t5gcon tmr5ge t5gpol t5gtm t5gspm t5ggo/done t5gval t5gss<1:0> 169 tmr1l holding register for the least significant byte of the 16-bit tmr1 regist er 164* tmr3l holding register for the least significant byte of the 16-bit tmr3 regist er 164* tmr6l holding register for the least significant byte of the 16-bit tmr6 regist er 164* tmr1h holding register for the most significant byte of the 16-bit tmr1 register 164* tmr3h holding register for the most significant byte of the 16-bit tmr3 register 164* tmr6h holding register for the most significant byte of the 16-bit tmr6 register 164* trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 114 legend: = unimplemented location, read as 0 . shaded cells are not used by capture mode. * page provides register information. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 180 ? 2011-2015 microchip technology inc. 20.2 compare mode the compare mode function described in this section is available and identical for ccp modules. compare mode makes use of the 16-bit timer1/3/5 resource. the 16-bit value of the ccprxh:ccprxl register pair is constantly compared against the 16-bit value of the tmrxh:tmrxl register pair. when a match occurs, one of the following events can occur: toggle the ccpx output set the ccpx output clear the ccpx output generate a special event trigger generate a software interrupt the action on the pin is based on the value of the ccpxm<3:0> control bits of the ccpxcon register. at the same time, the interrupt flag ccpxif bit is set. all compare modes can generate an interrupt. figure 20-2 shows a simplified diagram of the compare operation. figure 20-2: compare mode operation block diagram 20.2.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the associated tris bit. also, the ccpx pin function can be moved to alternative pins using the apfcon register. refer to section 12.1 ?alternate pin function? for more details. 20.2.2 timer1/3/5 mode resource in compare mode, timer1/3/5 must be running in either timer mode or synchronized counter mode. the compare operation may not work in asynchronous counter mode. see section 18.0 ?timer1/3/5 module with gate control? for more information on configuring timer1/3/5. ccprxh ccprxl tmrxh tmrxl comparator qs r output logic special event trigger set ccpxif interrupt flag (pirx) match tris ccpxm<3:0> mode select output enable pin ccpx 4 note: clearing the ccpxcon register will force the ccpx compare output latch to the default low level. this is not the port i/o data latch. table 20-3: ccpx compare timer1/3/5 resources ccp tmr1 tmr3 tmr5 ccp1 ccp2 ccp3 ccp4 ccp5 ccp6 ccp7 ccp8 ccp9 ccp10 note: clocking timer1/3/5 from the system clock (f osc ) should not be used in compare mode. in order for compare mode to recognize the trigger event on the ccpx pin, timer1/3/5 must be clocked from the instruction clock (f osc /4) or from an external clock source. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 181 pic16(l)f1526/7 20.2.3 software interrupt mode when generate software interrupt mode is chosen (ccpxm<3:0> = 1010 ), the ccpx module does not assert control of the ccpx pin (see the ccpxcon register). 20.2.4 special event trigger when special event trigger mode is chosen (ccpxm<3:0> = 1011 ), the ccpx module does the following: resets timer1/3/5 starts an adc conversion if adc is enabled the ccpx module does not assert control of the ccpx pin in this mode. the special event trigger output of the ccp occurs immediately upon a match between the tmrxh, tmrxl register pair and the ccprxh, ccprxl regis- ter pair. the tmrxh, tmrxl register pair is not reset until the next rising edge of the timer1/3/5 clock. the special event trigger output starts an adc conversion (if the adc module is enabled). this allows the ccprxh, ccprxl register pair to effectively provide a 16-bit programmable period register for timer1/3/5. refer to section 16.2.5 ?special event trigger? for more information. 20.2.5 compare during sleep the compare mode is dependent upon the system clock (f osc ) for proper operation. since f osc is shut down during sleep mode, the compare mode will not function properly during sleep. 20.2.6 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 20-4: special event trigger device ccpx pic16(l)f1526/7 ccp10 note 1: the special event trigger from the ccp module does not set interrupt flag bit tmrxif of the pirx register. 2: removing the match condition by changing the contents of the ccprxh and ccprxl register pair, between the clock edge that generates the special event trigger and the clock edge that generates the timer1/3/5 reset, will preclude the reset from occurring. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 182 ? 2011-2015 microchip technology inc. table 20-5: summary of regist ers associated with compare name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon t3ckisel ccp2sel 112 ccp1con dc1b<1:0> ccp1m<3:0> 189 ccp2con dc2b<1:0> ccp2m<3:0> 189 ccp3con dc3b<1:0> ccp3m<3:0> 189 ccp4con dc4b<1:0> ccp4m<3:0> 189 ccp5con dc5b<1:0> ccp5m<3:0> 189 ccp6con dc6b<1:0> ccp6m<3:0> 189 ccp7con dc7b<1:0> ccp7m<3:0> 189 ccp8con dc8b<1:0> ccp8m<3:0> 189 ccp9con dc9b<1:0> ccp9m<3:0> 189 ccp10con dc10b<1:0> ccp10m<3:0> 189 ccpr1l capture/compare/pwm register 1 low byte (lsb) 176* ccpr2l capture/compare/pwm register 2 low byte (lsb) 176* ccpr3l capture/compare/pwm register 3 low byte (lsb) 176* ccpr4l capture/compare/pwm register 4 low byte (lsb) 176* ccpr5l capture/compare/pwm register 5 low byte (lsb) 176* ccpr6l capture/compare/pwm register 6 low byte (lsb) 176* ccpr7l capture/compare/pwm register 7 low byte (lsb) 176* ccpr8l capture/compare/pwm register 8 low byte (lsb) 176* ccpr9l capture/compare/pwm register 9 low byte (lsb) 176* ccpr10l capture/compare/pwm register 10 low byte (lsb) 176* ccpr1h capture/compare/pwm register 1 high byte (msb) 176* ccpr2h capture/compare/pwm register 2 high byte (msb) 176* ccpr3h capture/compare/pwm register 3 high byte (msb) 176* ccpr4h capture/compare/pwm register 4 high byte (msb) 176* ccpr5h capture/compare/pwm register 5 high byte (msb) 176* ccpr6h capture/compare/pwm register 6 high byte (msb) 176* ccpr7h capture/compare/pwm register 7 high byte (msb) 176* ccpr8h capture/compare/pwm register 8 high byte (msb) 176* ccpr9h capture/compare/pwm register 9 high byte (msb) 176* ccpr10h capture/compare/pwm register 10 high byte (msb) 176* intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 78 pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 79 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 83 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync tmr1on 168 t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync tmr3on 168 t5con tmr5cs<1:0> t5ckps<1:0> soscen t5sync tmr5on 168 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 169 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/done t3gval t3gss<1:0> 169 legend: = unimplemented location, read as 0 . shaded cells are not used by compare mode. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 183 pic16(l)f1526/7 table 20-5: summary of registers as sociated with compare (continued) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page t5gcon tmr5ge t5gpol t5gtm t5gspm t5ggo/done t5gval t5gss<1:0> 169 tmr1l holding register for the least significant byte of the 16-bit tmr1 regist er 164* tmr3l holding register for the least significant byte of the 16-bit tmr3 regist er 164* tmr6l holding register for the least significant byte of the 16-bit tmr6 regist er 164* tmr1h holding register for the most significant byte of the 16-bit tmr1 register 164* tmr3h holding register for the most significant byte of the 16-bit tmr3 register 164* tmr6h holding register for the most significant byte of the 16-bit tmr6 register 164* trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 114 legend: = unimplemented location, read as 0 . shaded cells are not used by compare mode. * page provides register information. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 184 ? 2011-2015 microchip technology inc. 20.3 pwm overview pulse-width modulation (pwm) is a scheme that provides power to a load by switching quickly between fully on and fully off states. the pwm signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. the high portion, also known as the pulse width, can vary in time and is defined in steps. a larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. lowering the number of steps applied, which shortens the pulse width, supplies less power. the pwm period is defined as the duration of one complete cycle or the total amount of on and off time combined. pwm resolution defines the maximum number of steps that can be present in a single pwm period. a higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. the term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. a lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. figure 20-3 shows a typical waveform of the pwm signal. 20.3.1 standard pwm operation the standard pwm function described in this section is available and identical for ccp modules. the standard pwm mode generates a pulse-width modulation (pwm) signal on the ccpx pin with up to 10 bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: prx registers txcon registers ccprxl registers ccpxcon registers figure 20-4 shows a simplified block diagram of pwm operation. figure 20-3: ccp pwm output signal figure 20-4: simplified pwm block diagram note 1: the corresponding tris bit must be cleared to enable the pwm output on the ccpx pin. 2: clearing the ccpxcon register will relinquish control of the ccpx pin. table 20-6: ccpx pwm timer2/4/6/8/10 resources ccp tmr2 tmr4 tm r6 tmr8 tmr10 ccp1 ccp2 ccp3 ccp4 ccp5 ccp6 ccp7 ccp8 ccp9 ccp10 period pulse width tmrx = 0 tmrx = ccprxh:ccpxcon<5:4> tmrx = prx ccprxl ccprxh (2) (slave) comparator tmrx prx (1) rq s duty cycle registers ccpxcon<5:4> clear timer, toggle ccpx pin and latch duty cycle note 1: the 8-bit timer tmrx register is concatenated with the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. 2: in pwm mode, ccprxh is a read-only register. tris ccpx comparator downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 185 pic16(l)f1526/7 20.3.2 setup for pwm operation the following steps should be taken when configuring the ccp module for standard pwm operation: 1. disable the ccpx pin output driver by setting the associated tris bit. 2. load the prx register with the pwm period value. 3. configure the ccp module for the pwm mode by loading the ccpxcon register with the appropriate values. 4. load the ccprxl register and the dcxbx bits of the ccpxcon register, with the pwm duty cycle value. 5. configure and start timer2/4/6/8/10: select the timer2/4/6/8/10 resource to be used for pwm generation by setting the cxtsel<1:0> bits in the ccptmrsx register. clear the tmrxif interrupt flag bit of the pirx register. see note below. configure the txckps bits of the txcon register with the timer prescale value. enable the timer by setting the tmrxon bit of the txcon register. 6. enable pwm output pin: wait until the timer overflows and the tmrxif bit of the pirx register is set. see note below. enable the ccpx pin output driver by clearing the associated tris bit. 20.3.3 timer2/4/6/8/10 timer resource the pwm standard mode makes use of one of the 8-bit timer2/4/6/8/10 timer resources to specify the pwm period. configuring the cxtsel<1:0> bits in the ccptmrsx register selects which timer2/4/6/8/10 timer is used. see ta b l e 2 0 - 6 for ccpx pwm timer2/4/6/8/10 resources. 20.3.4 pwm period the pwm period is specified by the prx register of timer2/4/6/8/10. the pwm period can be calculated using the formula of equation 20-1 . equation 20-1: pwm period when tmrx is equal to prx, the following three events occur on the next increment cycle: tmrx is cleared the ccpx pin is set. (exception: if the pwm duty cycle = 0%, the pin will not be set.) the pwm duty cycle is latched from ccprxl into ccprxh. note: in order to send a complete duty cycle and period on the first pwm output, the above steps must be included in the setup sequence. if it is not critical to start with a complete pwm signal on the first output, then step 6 may be ignored. note: the timer postscaler (see section 19.1 ?timer2/4/6/8/10 operation? is not used in the determination of the pwm frequency. pwm period prx ?? 1+ ?? 4t osc ? ? ? = (tmrx prescale value) note 1: t osc = 1/f osc downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 186 ? 2011-2015 microchip technology inc. 20.3.5 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to multiple registers: ccprxl register and dcxb<1:0> bits of the ccpxcon register. the ccprxl contains the eight msbs and the dcxb<1:0> bits of the ccpxcon register contain the two lsbs. ccprxl and dcxb<1:0> bits of the ccpxcon register can be written to at any time. the duty cycle value is not latched into ccprxh until after the period completes (i.e., a match between prx and tmrx registers occurs). while using the pwm, the ccprxh register is read-only. equation 20-2 is used to calculate the pwm pulse width. equation 20-3 is used to calculate the pwm duty cycle ratio. equation 20-2: pulse width equation 20-3: duty cycle ratio the ccprxh register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. the 8-bit timer tmrx register is concatenated with either the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2/4/6/8/10 prescaler is set to 1:1. when the 10-bit time base matches the ccprxh and 2-bit latch, then the ccpx pin is cleared (see figure 20-4 ). 20.3.6 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is 10 bits when prx is 255. the resolution is a function of the prx register value as shown by equation 20-4 . equation 20-4: pwm resolution table 20-7: example pwm frequencies and resolutions (f osc = 20 mhz) table 20-8: example pwm frequencies and resolutions (f osc = 8 mhz) pulse width ccprxl:ccpxcon<5:4> ?? ? = t osc ? (tmrx prescale value) duty cycle ratio ccprxl:ccpxcon<5:4> ?? 4 prx 1 + ?? ---------------------------------------------------------------------- - = note: if the pulse width value is greater than the period the assigned pwm pin(s) will remain unchanged. resolution 4prx 1 + ?? ?? log 2 ?? log ----------------------------------------- - bits = pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 prx value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 prx value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 187 pic16(l)f1526/7 20.3.7 operation in sleep mode in sleep mode, the tmrx register will not increment and the state of the module will not change. if the ccpx pin is driving a value, it will continue to drive that value. when the device wakes up, tmrx will continue from its previous state. 20.3.8 changes in system clock frequency the pwm frequency is derived from the system clock frequency. any changes in the system clock frequency will result in changes to the pwm frequency. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for additional details. 20.3.9 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. 20.3.10 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 20-9: summary of registers associated with standard pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon t3ckisel ccp2sel 112 ccp1con dc1b<1:0> ccp1m<3:0> 189 ccp2con dc2b<1:0> ccp2m<3:0> 189 ccp3con dc3b<1:0> ccp3m<3:0> 189 ccp4con dc4b<1:0> ccp4m<3:0> 189 ccp5con dc5b<1:0> ccp5m<3:0> 189 ccp6con dc6b<1:0> ccp6m<3:0> 189 ccp7con dc7b<1:0> ccp7m<3:0> 189 ccp8con dc8b<1:0> ccp8m<3:0> 189 ccp9con dc9b<1:0> ccp9m<3:0> 189 ccp10con dc10b<1:0> ccp10m<3:0> 189 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 78 pie3 ccp6ie ccp5ie ccp4ie ccp3ie tmr6ie tmr5ie tmr4ie tmr3ie 79 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 pir3 ccp6if ccp5if ccp4if ccp3if tmr6if tmr5if tmr4if tmr3if 83 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 pr2 timer2 period register 171* pr4 timer4 period register 171* pr6 timer6 period register 171* pr8 timer8 period register 171* pr10 timer10 period register 171* t2con t2outps<3:0> tmr2on t2ckps<:0>1 168 t4con t4outps<3:0> tmr4on t4ckps<:0>1 168 t6con t6outps<3:0> tmr6on t6ckps<:0>1 168 legend: = unimplemented location, read as 0 . shaded cells are not used by the pwm. * page provides register information. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 188 ? 2011-2015 microchip technology inc. table 20-10: summary of registers asso ciated with standard pwm (continued) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page t8con t8outps<3:0> tmr8on t8ckps<:0>1 168 t10con t10outps<3:0> tmr10on t10ckps<:0>1 168 tmr2 timer2 module register 171* tmr4 timer4 module register 171* tmr6 timer6 module register 171* tmr8 timer8 module register 171* tmr10 timer10 module register 171* trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 114 legend: = unimplemented location, read as 0 . shaded cells are not used by the pwm. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 189 pic16(l)f1526/7 20.4 register definitions: eccp control register 20-1: ccpxcon: ccpx control register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 dcxb<1:0> ccpxm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-4 dcxb<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm<3:0>: ccpx mode select bits 11xx =pwm mode 1011 = compare mode: special event trigger (sets ccp10if bit (ccp10), starts adc conversion if adc module is enabled) (1) 1010 = compare mode: generate software interrupt only 1001 = compare mode: clear output on compare match (set ccpxif) 1000 = compare mode: set output on compare match (set ccpxif) 0111 = capture mode: every 16th rising edge 0110 = capture mode: every 4th rising edge 0101 = capture mode: every rising edge 0100 = capture mode: every falling edge 0011 = reserved 0010 = compare mode: toggle output on match 0001 = reserved 0000 = capture/compare/pwm off (resets ccpx module) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 190 ? 2011-2015 microchip technology inc. register 20-2: ccptmrs0: ccp time r selection control register 0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 c4tsel<1:0> c3tsel<1:0> c2tsel<1:0> c1tsel<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 c4tsel<1:0>: ccp4 timer selection bits when in capture/compare mode : x1 = ccp4 is based off timer3 in capture/compare mode x0 = ccp4 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp4 is based off timer6 in pwm mode 01 = ccp4 is based off timer4 in pwm mode 00 = ccp4 is based off timer2 in pwm mode bit 5-4 c3tsel<1:0>: ccp3 timer selection bits when in capture/compare mode : x1 = ccp3 is based off timer3 in capture/compare mode x0 = ccp3 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp3 is based off timer6 in pwm mode 01 = ccp3 is based off timer4 in pwm mode 00 = ccp3 is based off timer2 in pwm mode bit 3-2 c2tsel<1:0>: ccp2 timer selection bits when in capture/compare mode : x1 = ccp2 is based off timer3 in capture/compare mode x0 = ccp2 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp2 is based off timer6 in pwm mode 01 = ccp2 is based off timer4 in pwm mode 00 = ccp2 is based off timer2 in pwm mode bit 1-0 c1tsel<1:0>: ccp1 timer selection bits when in capture/compare mode : x1 = ccp1 is based off timer3 in capture/compare mode x0 = ccp1 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp1 is based off timer6 in pwm mode 01 = ccp1 is based off timer4 in pwm mode 00 = ccp1 is based off timer2 in pwm mode downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 191 pic16(l)f1526/7 register 20-3: ccptmrs1: ccp time r selection control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 c8tsel<1:0> c7tsel<1:0> c6tsel<1:0> c5tsel<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 c8tsel<1:0>: ccp8 timer selection bits when in capture/compare mode : x1 = ccp8 is based off timer5 in capture/compare mode x0 = ccp8 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp8 is based off timer10 in pwm mode 01 = ccp8 is based off timer8 in pwm mode 00 = ccp8 is based off timer2 in pwm mode bit 5-4 c7tsel<1:0>: ccp7 timer selection bits when in capture/compare mode : x1 = ccp7 is based off timer5 in capture/compare mode x0 = ccp7 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp7 is based off timer8 in pwm mode 01 = ccp7 is based off timer6 in pwm mode 00 = ccp7 is based off timer2 in pwm mode bit 3-2 c6tsel<1:0>: ccp6 timer selection bits when in capture/compare mode : x1 = ccp6 is based off timer5 in capture/compare mode x0 = ccp6 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp6 is based off timer8 in pwm mode 01 = ccp6 is based off timer6 in pwm mode 00 = ccp6 is based off timer2 in pwm mode bit 1-0 c5tsel<1:0>: ccp5 timer selection bits when in capture/compare mode : x1 = ccp5 is based off timer5 in capture/compare mode x0 = ccp5 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp5 is based off timer8 in pwm mode 01 = ccp5 is based off timer6 in pwm mode 00 = ccp5 is based off timer2 in pwm mode downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 192 ? 2011-2015 microchip technology inc. register 20-4: ccptmrs2: ccp time r selection control register 2 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 c10tsel<1:0> c9tsel<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-2 c10tsel<1:0>: ccp10 timer selection bits when in capture/compare mode : x1 = ccp10 is based off timer5 in capture/compare mode x0 = ccp10 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp10 is based off timer10 in pwm mode 01 = ccp10 is based off timer8 in pwm mode 00 = ccp10 is based off timer2 in pwm mode bit 1-0 c9tsel<1:0>: ccp9 timer selection bits when in capture/compare mode : x1 = ccp9 is based off timer5 in capture/compare mode x0 = ccp9 is based off timer1 in capture/compare mode w hen in pwm mode : 11 =reserved 10 = ccp9 is based off timer10 in pwm mode 01 = ccp9 is based off timer8 in pwm mode 00 = ccp9 is based off timer2 in pwm mode downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 193 pic16(l)f1526/7 21.0 master synchronous serial port (mssp1 and mssp2) module 21.1 master sspx (msspx) module overview the master synchronous serial port (msspx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the msspx module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) the spi interface supports the following modes and features: master mode slave mode clock parity slave select synchronization (slave mode only) daisy-chain connection of slave devices figure 21-1 is a block diagram of the spi interface module. figure 21-1: msspx bloc k diagram (spi mode) ( ) read write data bus sspxsr reg sspm<3:0> bit 0 shift clock ssx control enable edge select clock select tmr2 output 2 edge select 2 (ckp, cke) 4 tris bit sdox sspxbuf reg sdix ssx sckx t osc prescaler 4, 16, 64 baud rate generator (sspxadd) sdo_out sck_out downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 194 ? 2011-2015 microchip technology inc. the i 2 c interface supports the following modes and features: master mode slave mode byte nacking (slave mode) limited multi-master support 7-bit and 10-bit addressing start and stop interrupts interrupt masking clock stretching bus collision detection general call address matching address masking address hold and data hold modes selectable sdax hold times figure 21-2 is a block diagram of the i 2 c interface module in master mode. figure 21-3 is a diagram of the i 2 c interface module in slave mode. the pic16f1527 has two mssp modules, mssp1 and mssp2, each module operating independently from the other. figure 21-2: msspx block diagram (i 2 c master mode) note 1: in devices with more than one mssp module, it is very important to pay close attention to sspxconx register names. ssp1con1 and ssp1con2 registers control different operational aspects of the same module, while ssp1con1 and ssp2con1 control the same features for two different modules. 2: throughout this section, generic refer- ences to an mssp module in any of its operating modes may be interpreted as being equally applicable to mssp1 or mssp2. register names, module i/o sig- nals, and bit names may use the generic designator x to indicate the use of a numeral to distinguish a particular module when required. read write sspxsr start bit, stop bit, start bit detect, sspxbuf internal data bus set/reset: s, p, sspxstat, wcol, sspov shift clock msb lsb sdax acknowledge generate (sspxcon2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv sclx sclx in bus collision sdax in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [sspm 3:0] baud rate reset sen, pen (sspxcon2) generator (sspxadd) address match detect set sspxif, bclxif downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 195 pic16(l)f1526/7 figure 21-3: msspx block diagram (i 2 c slave mode) read write sspxsr reg match detect sspxadd reg start and stop bit detect sspxbuf reg internal data bus addr match set, reset s, p bits (sspxstat reg) sclx sdax shift clock msb lsb sspxmsk reg downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 196 ? 2011-2015 microchip technology inc. 21.2 spi mode overview the serial peripheral interface (spi) bus is a synchronous serial data communication bus that operates in full-duplex mode. devices communicate in a master/slave environment where the master device initiates the communication. a slave device is controlled through a chip select known as slave select. the spi bus specifies four signal connections: serial clock (sckx) serial data out (sdox) serial data in (sdix) slave select (ssx ) figure 21-1 shows the block diagram of the msspx module when operating in spi mode. the spi bus operates with a single master device and one or more slave devices. when multiple slave devices are used, an independent slave select con- nection is required from the master device to each slave device. figure 21-4 shows a typical connection between a master device and multiple slave devices. the master selects only one slave at a time. most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. with either the master or the slave device, data is always shifted out one bit at a time, with the most significant bit (msb) shifted out first. at the same time, a new least significant bit (lsb) is shifted into the same register. figure 21-5 shows a typical connection between two processors configured as master and slave devices. data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. the master device transmits information out on its sdox output pin which is connected to, and received by, the slaves sdix input pin. the slave device transmits information out on its sdox output pin, which is connected to, and received by, the masters sdix input pin. to begin communication, the master device first sends out the clock signal. both the master and the slave devices should be configured for the same clock polarity. the master device starts a transmission by sending out the msb from its shift register. the slave device reads this bit from that same line and saves it into the lsb position of its shift register. during each spi clock cycle, a full-duplex data transmission occurs. this means that while the master device is sending out the msb from its shift register (on its sdox pin) and the slave device is reading this bit and saving it as the lsb of its shift register, that the slave device is also sending out the msb from its shift register (on its sdox pin) and the master device is reading this bit and saving it as the lsb of its shift register. after 8 bits have been shifted out, the master and slave have exchanged register values. if there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. whether the data is meaningful or not (dummy data), depends on the application software. this leads to three scenarios for data transmission: master sends useful data and slave sends dummy data. master sends useful data and slave sends useful data. master sends dummy data and slave sends useful data. transmissions may involve any number of clock cycles. when there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. every slave device connected to the bus that has not been selected through its slave select line must disre- gard the clock and transmission signals and must not transmit out any data of its own. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 197 pic16(l)f1526/7 figure 21-4: spi master and multiple slave connection 21.2.1 spi mode registers the msspx module has five registers for spi mode operation. these are: msspx status register (sspxstat) msspx control register 1 (sspxcon1) msspx control register 3 (sspxcon3) msspx data buffer register (sspxbuf) msspx address register (sspxadd) msspx shift register (sspxsr) (not directly accessible) sspxcon1 and sspxstat are the control and status registers in spi mode operation. the sspx- con1 register is readable and writable. the lower 6 bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. in one spi master mode, sspxadd can be loaded with a value used in the baud rate generator. more information on the baud rate generator is available in section 21.7 ?baud rate generator? . sspxsr is the shift register used for shifting data in and out. sspxbuf provides indirect access to the sspxsr register. sspxbuf is the buffer register to which data bytes are written, and from which data bytes are read. in receive operations, sspxsr and sspxbuf together create a buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspxif interrupt is set. during transmission, the sspxbuf is not buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. spi master sckx sdox sdix general i/o general i/o general i/o sckxsdix sdox ssx spi slave #1 sckxsdix sdox ssx spi slave #2 sckxsdix sdox ssx spi slave #3 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 198 ? 2011-2015 microchip technology inc. 21.2.2 spi mode operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspxcon1<5:0> and sspxstat<7:6>). these control bits allow the following to be specified: master mode (sckx is the clock output) slave mode (sckx is the clock input) clock polarity (idle state of sckx) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sckx) clock rate (master mode only) slave select mode (slave mode only) to enable the serial port, sspx enable bit, sspen of the sspxcon1 register, must be set. to reset or recon- figure spi mode, clear the sspen bit, re-initialize the sspxconx registers and then set the sspen bit. this configures the sdix, sdox, sckx and ssx pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: sdix must have corresponding tris bit set sdox must have corresponding tris bit cleared sckx (master mode) must have corresponding tris bit cleared sckx (slave mode) must have corresponding tris bit set ssx must have corresponding tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. the msspx consists of a transmit/receive shift register (sspxsr) and a buffer register (sspxbuf). the sspxsr shifts the data in and out of the device, msb first. the sspxbuf holds the data that was written to the sspxsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspxbuf register. then, the buffer full detect bit, bf of the sspxstat register, and the interrupt flag bit, sspxif, are set. this double-buffering of the received data (sspxbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspxbuf register during transmission/reception of data will be ignored and the write collision detect bit wcol of the sspxcon1 register, will be set. user software must clear the wcol bit to allow the following write(s) to the sspxbuf register to complete successfully. when the application software is expecting to receive valid data, the sspxbuf should be read before the next byte of data to transfer is written to the sspxbuf. the buffer full bit, bf of the sspxstat register, indicates when sspxbuf has been loaded with the received data (transmission is complete). when the sspxbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the msspx interrupt is used to determine when the transmission/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. figure 21-5: spi mast er/slave connection serial input buffer (buf) shift register (sspxsr) msb lsb sdox sdix processor 1 sckx spi master sspm<3:0> = 00xx serial input buffer (sspxbuf) shift register (sspxsr) lsb msb sdix sdox processor 2 sckx spi slave sspm<3:0> = 010x serial clock ssx slave select general i/o (optional) = 1010 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 199 pic16(l)f1526/7 21.2.3 spi master mode the master can initiate the data transfer at any time because it controls the sckx line. the master determines when the slave (processor 2, figure 21-5 ) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspxbuf register is written to. if the spi is only going to receive, the sdox output could be dis- abled (programmed as an input). the sspxsr register will continue to shift in the signal present on the sdix pin at the programmed clock rate. as each byte is received, it will be loaded into the sspxbuf register as if a normal received byte (interrupts and status bits appropriately set). the clock polarity is selected by appropriately programming the ckp bit of the sspxcon1 register and the cke bit of the sspxstat register. this then, would give waveforms for spi communication as shown in figure 21-6 , figure 21-8 , figure 21-9 and figure 21-10 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 * t cy ) f osc /64 (or 16 * t cy ) timer2 output/2 fosc/(4 * (sspxadd + 1)) figure 21-6 shows the waveforms for master mode. when the cke bit is set, the sdox data is valid before there is a clock edge on sckx. the change of the input sample is shown based on the state of the smp bit. the time when the sspxbuf is loaded with the received data is shown. figure 21-6: spi mode waveform (master mode) sckx (ckp = 0 sckx (ckp = 1 sckx (ckp = 0 sckx (ckp = 1 4 clock modes input sample input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdix sspxif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) bit 0 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 200 ? 2011-2015 microchip technology inc. 21.2.4 spi slave mode in slave mode, the data is transmitted and received as external clock pulses appear on sckx. when the last bit is latched, the sspxif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sckx pin. the idle state is determined by the ckp bit of the sspxcon1 register. while in slave mode, the external clock is supplied by the external clock source on the sckx pin. this exter- nal clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. the shift register is clocked from the sckx pin input and when a byte is received, the device will generate an interrupt. if enabled, the device will wake-up from sleep. 21.2.4.1 daisy-chain configuration the spi bus can sometimes be connected in a daisy-chain configuration. the first slave output is con- nected to the second slave input, the second slave output is connected to the third slave input, and so on. the final slave output is connected to the master input. each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. the whole chain acts as one large communication shift register. the daisy-chain feature only requires a single slave select line from the master device. figure 21-7 shows the block diagram of a typical daisy-chain connection when operating in spi mode. in a daisy-chain configuration, only the most recent byte on the bus is required by the slave. setting the boen bit of the sspxcon3 register will enable writes to the sspxbuf register, even if the previous byte has not been read. this allows the software to ignore data that may not apply to it. 21.2.5 slave select synchronization the slave select can also be used to synchronize communication. the slave select line is held high until the master device is ready to communicate. when the slave select line is pulled low, the slave knows that a new transmission is starting. if the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the slave select line returns to a high state. the slave is then ready to receive a new transmission when the slave select line is pulled low again. if the slave select line is not used, there is a risk that the slave will eventually become out of sync with the master. if the slave misses a bit, it will always be one bit off in future transmissions. use of the slave select line allows the slave and master to align themselves at the beginning of each transmission. the ssx pin allows a synchronous slave mode. the spi must be in slave mode with ssx pin control enabled (sspxcon1<3:0> = 0100 ). when the ssx pin is low, transmission and reception are enabled and the sdox pin is driven. when the ssx pin goes high, the sdox pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the applica- tion. when the spi module resets, the bit counter is forced to 0 . this can be done by either forcing the ssx pin to a high level or clearing the sspen bit. note 1: when the spi is in slave mode with ssx pin control enabled (sspxcon1<3:0> = 0100 ), the spi module will reset if the ssx pin is set to v dd . 2: when the spi is used in slave mode with cke set; the user must enable ssx pin control. 3: while operated in spi slave mode the smp bit of the sspxstat register must remain clear. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 201 pic16(l)f1526/7 figure 21-7: spi daisy-chain connection figure 21-8: slave sele ct synchronous waveform spi master sck sdox sdix general i/o scksdix sdox ssx spi slave #1 scksdix sdox ssx spi slave #2 scksdix sdox ssx spi slave #3 sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 7 sspxif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag bit 0 bit 7 bit 0 bit 6 sspxbuf to sspxsr shift register sspxsr and bit count are reset downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 202 ? 2011-2015 microchip technology inc. figure 21-9: spi mode wavefo rm (slave mode with cke = 0 ) figure 21-10: spi mode waveform (slave mode with cke = 1 ) sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag optional bit 0 detection active write collision valid sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt cke = 1 ) cke = 1 ) write to sspxbuf sspxsr to sspxbuf ssx flag not optional write collision detection active valid downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 203 pic16(l)f1526/7 21.2.6 spi operation in sleep mode in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the sleep mode, all clocks are halted. special care must be taken by the user when the msspx clock is much faster than the system clock. in slave mode, when msspx interrupts are enabled, after the master completes sending data, an msspx interrupt will wake the controller from sleep. if an exit from sleep mode is not desired, msspx interrupts should be disabled. in spi master mode, when the sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the msspx interrupt flag bit will be set and if enabled, will wake the device. table 21-1: summary of registers as sociated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anself ansf7 ansf6 ansf5 ansf4 ansf3 ansf2 ansf1 ansf0 130 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 ssp1buf msspx receive buffer/transmit register 197* ssp2buf msspx receive buffer/transmit register 197* ssp1con1 wcol sspov sspen ckp sspm<3:0> 244 ssp2con1 wcol sspov sspen ckp sspm<3:0> 244 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 246 ssp2con3 acktim pcie scie boen sdaht sbcde ahen dhen 246 ssp1stat smp cke d/a psr / w ua bf 242 ssp2stat smp cke d/a psr / w ua bf 242 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 123 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 129 legend: = unimplemented location, read as 0 . shaded cells are not used by the msspx in spi mode. * page provides register information. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 204 ? 2011-2015 microchip technology inc. 21.3 i 2 c mode overview the inter-integrated circuit bus (i 2 c) is a multi-master serial data communication bus. devices communicate in a master/slave environment where the master devices initiate the communication. a slave device is controlled through addressing. the i 2 c bus specifies two signal connections: serial clock (sclx) serial data (sdax) figure 21-2 and figure 21-3 shows the block diagram of the msspx module when operating in i 2 c mode. both the sclx and sdax connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. figure 21-11 shows a typical connection between two processors configured as master and slave devices. the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: master transmit mode (master is transmitting data to a slave) master receive mode (master is receiving data from a slave) slave transmit mode (slave is transmitting data to a master) slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a sin- gle read/write bit, which determines whether the mas- ter intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the comple- ment, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sdax line while the sclx line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. figure 21-11: i 2 c master/ slave connection the acknowledge bit (ack ) is an active-low signal, which holds the sdax line low to indicate to the trans- mitter that the slave device has received the transmit- ted data and is ready to receive more. the transition of a data bit is always performed while the sclx line is held low. transitions that occur while the sclx line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeat- edly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this exam- ple, the master device is in master receive mode and the slave is slave transmit mode. on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indi- cated by a low-to-high transition of the sdax line while the sclx line is held high. in some cases, the master may want to maintain con- trol of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols; single message where a master writes data to a slave. single message where a master reads data from a slave. combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. master sclx sdax sclxsdax slave v dd v dd downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 205 pic16(l)f1526/7 when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the sclx line, is called clock stretching. clock stretching gives slave devices a mechanism to control the flow of data. when this detection is used on the sdax line, it is called arbitration. arbitration ensures that there is only one master device communicating at any single time. 21.3.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the sclx clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. the master that is communicating with the slave will attempt to raise the sclx line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the sclx connec- tion is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 21.3.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a transmission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sdax data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the sdax line. for example, if one transmitter holds the sdax line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sdax line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sdax line. if this transmitter is also a master device, it also must stop driving the sclx line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sdax line continues with its original transmission. it can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. if two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 206 ? 2011-2015 microchip technology inc. 21.4 i 2 c mode operation all msspx i 2 c communication is byte oriented and shifted out msb first. six sfr registers and 2 interrupt flags interface the module with the pic ? microcontrol- ler and user software. two pins, sdax and sclx, are exercised by the module to communicate with other external i 2 c devices. 21.4.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, fol- lowed by an acknowledge bit sent back. after the 8th falling edge of the sclx line, the device outputting data on the sdax changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, sclx, is provided by the master. data is valid to change while the sclx signal is low, and sampled on the rising edge of the clock. changes on the sdax line while the sclx line is high define special conditions on the bus, explained below. 21.4.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explanation. this table was adapted from the philips i 2 c specification. 21.4.3 sdax and sclx pins selection of any i 2 c mode with the sspen bit set, forces the sclx and sdax pins to be open-drain. these pins should be set by the user to inputs by set- ting the appropriate tris bits. 21.4.4 sdax hold time the hold time of the sdax pin is selected by the sdaht bit of the sspxcon3 register. hold time is the time sdax is held valid after the falling edge of sclx. setting the sdaht bit selects a longer 300 ns mini- mum hold time and may help on buses with large capacitance. table 21-2: i 2 c bus terms note: data is tied to output zero when an i 2 c mode is enabled. term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and terminates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sdax and sclx lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in sspxadd. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus hold sclx low to stall communication. bus collision any time the sdax line is sampled low by the module while it is out- putting and expected high state. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 207 pic16(l)f1526/7 21.4.5 start condition the i 2 c specification defines a start condition as a transition of sdax from a high to a low state while sclx line is high. a start condition is always gener- ated by the master and signifies the transition of the bus from an idle to an active state. figure 21-12 shows wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sdax line low before asserting it low. this does not conform to the i 2 c specification that states no bus collision can occur on a start. 21.4.6 stop condition a stop condition is a transition of the sdax line from low-to-high state while the sclx line is high. 21.4.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. figure 21-13 shows the wave form for a restart condition. in 10-bit addressing slave mode a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, match- ing both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained. until a stop condi- tion, a high address with r/w clear, or high address match fails. 21.4.8 start/stop condition interrupt masking the scie and pcie bits of the sspxcon3 register can enable the generation of an interrupt in slave modes that do not typically support this function. slave modes where interrupt on start and stop detect are already enabled, these bits will have no effect. figure 21-12: i 2 c start and stop conditions note: at least one sclx low time must appear before a stop is valid, therefore, if the sdax line goes low then high again while the sclx line stays high, only the start condition is detected. sdax sclx p stop condition s start condition change of data allowed change of data allowed downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 208 ? 2011-2015 microchip technology inc. figure 21-13: i 2 c restart condition restart condition sr change of data allowed change of data allowed downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 209 pic16(l)f1526/7 21.4.9 acknowledge sequence the 9th sclx pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sdax line low. the transmitter must release con- trol of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pull- ing the sdax line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the sspxcon2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the sspxcon2 reg- ister is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the sspxcon3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the sspxstat regis- ter or the sspov bit of the sspxcon1 register are set when a byte is received. when the module is addressed, after the 8th falling edge of sclx on the bus, the acktim bit of the sspx- con3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim sta- tus bit is only active when the ahen bit or dhen bit is enabled. 21.5 i 2 c slave mode operation the msspx slave mode operates in one of four modes selected in the sspm bits of sspxcon1 regis- ter. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operated the same as the other modes with sspxif additionally getting set upon detection of a start, restart, or stop condition. 21.5.1 slave mode addresses the sspxadd register ( register 21-6 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspxbuf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the soft- ware that anything happened. the sspx mask register ( register 21-5 ) affects the address matching process. see section 21.5.9 ?sspx mask register? for more information. 21.5.1.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 21.5.1.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of 1 1 1 1 0 a9 a8 0. a9 and a8 are the two msbs of the 10-bit address and stored in bits 2 and 1 of the sspxadd register. after the acknowledge of the high byte the ua bit is set and sclx is held low until the user updates sspxadd with the low address. the low address byte is clocked in and all 8 bits are compared to the low address value in sspxadd. even if there is not an address match; sspxif and ua are set, and sclx is held low until sspxadd is updated to receive a high byte again. when sspxadd is updated the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hard- ware will then acknowledge the read request and pre- pare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 210 ? 2011-2015 microchip technology inc. 21.5.2 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the sspxstat register is cleared. the received address is loaded into the sspxbuf register and acknowledged. when the overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf of the sspxstat register is set, or bit sspov of the sspxcon1 register is set. the boen bit of the sspxcon3 register modifies this operation. for more information see register 21-4 . an msspx interrupt is generated for each transferred data byte. flag bit, sspxif, must be cleared by software. when the sen bit of the sspxcon2 register is set, sclx will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the sspxcon1 register, except sometimes in 10-bit mode. see section 21.2.3 ?spi master mode? for more detail. 21.5.2.1 7-bit addressing reception this section describes a standard sequence of events for the msspx module configured as an i 2 c slave in 7-bit addressing mode. figure 21-14 and figure 21-15 is used as a visual reference for this description. this is a step by step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sdax low sending an ack to the master, and sets sspxif bit. 5. software clears the sspxif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. if sen = 1 ; slave software sets ckp bit to release the sclx line. 8. the master clocks out a data byte. 9. slave drives sdax low sending an ack to the master, and sets sspxif bit. 10. software clears sspxif. 11. software reads the received byte from sspxbuf clearing bf. 12. steps 8-12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of sspxstat, and the bus goes idle. 21.5.2.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operate the same as without these options with extra interrupts and clock stretching added after the 8th fall- ing edge of sclx. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hard- ware. this functionality adds support for pmbus? that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communi- cation. figure 21-16 displays a module using both address and data holding. figure 21-17 includes the operation with the sen bit of the sspxcon2 register set. 1. s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. sspxif is set and ckp cleared after the 8th falling edge of sclx. 3. slave clears the sspxif. 4. slave can look at the acktim bit of the sspx- con3 register to determine if the sspxif was after or before the ack. 5. slave reads the address value from sspxbuf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. sspxif is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears sspxif. 11. sspxif set and ckp cleared after 8th falling edge of sclx for a received data byte. 12. slave looks at acktim bit of sspxcon3 to determine the source of the interrupt. 13. slave reads the received data from sspxbuf clearing bf. 14. steps 7-14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and interrupt on stop detect is disabled, the slave will only know by polling the p bit of the sststat register. note: sspxif is still set after the 9th falling edge of sclx even if there is no clock stretching and bf has been cleared. only if nack is sent to master is sspxif not set downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 211 pic16(l)f1526/7 figure 21-14: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx sspxif bf sspov 12345678 12345678 12345678 9 9 9 ack is not sent. sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf sspxbuf is read sspxif set on 9th falling edge of sclx cleared by software p bus master sends stop condition s from slave to master downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 212 ? 2011-2015 microchip technology inc. figure 21-15: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx 123456789 123456789 123456789 p sspxif set on 9th sclx is not held ckp is written to 1 in software, ckp is written to 1 in software, ack low because falling edge of sclx releasing sclx ack is not sent. bus master sends ckp sspov bf sspxif sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf ack = 1 cleared by software sspxbuf is read clock is held low until ckp is set to 1 releasing sclx stop condition s ack ack receive address receive data receive data r/w= 0 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 213 pic16(l)f1526/7 figure 21-16: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx bf ckp s p 12 3 4 56 7 8 9 12345678 9 12345678 master sends stop condition s data is read from sspxbuf cleared by software sspxif is set on 9th falling edge of sclx, after ack ckp set by software, sclx is released slave software 9 acktim cleared by hardware in 9th rising edge of sclx sets ackdt to not ack when dhen= 1 : ckp is cleared by hardware on 8th falling edge of sclx slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of sclx when ahen= 1 : ckp is cleared by hardware and sclx is stretched address is read from ssbuf acktim set by hardware on 8th falling edge of sclx ack master releases sdax to slave for ack sequence no interrupt after not ack from slave ack = 1 ack ackdt acktim sspxif if ahen = 1 : sspxif is set downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 214 ? 2011-2015 microchip technology inc. figure 21-17: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx sspxif bf ackdt ckp sp ack s 12 34 5678 9 12 3 4567 8 9 12 345 67 8 9 ack ack cleared by software acktim is cleared by hardware sspxbuf can be set by software, read any time before next byte is loaded release sclx on 9th rising edge of sclx received address is loaded into sspxbuf slave software clears ackdt to ack r/w = 0 master releases sdax to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of sclx of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of sclx when dhen = 1 ; on the 8th falling edge of sclx of a received data byte, ckp is cleared received data is available on sspxbuf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 215 pic16(l)f1526/7 21.5.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspxstat register is set. the received address is loaded into the sspxbuf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the sclx pin is held low (see section 21.5.6 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspxbuf register which also loads the sspxsr register. then the sclx pin should be released by setting the ckp bit of the sspxcon1 register. the eight data bits are shifted out on the falling edge of the sclx input. this ensures that the sdax signal is valid during the sclx high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth sclx input pulse. this ack value is copied to the ackstat bit of the sspxcon2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sdax line was low (ack ), the next transmit data must be loaded into the sspxbuf register. again, the sclx pin must be released by setting bit ckp. an msspx interrupt is generated for each data transfer byte. the sspxif bit must be cleared by software and the sspxstat register is used to determine the status of the byte. the sspxif bit is set on the falling edge of the ninth clock pulse. 21.5.3.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sdax line. if a bus collision is detected and the sbcde bit of the sspxcon3 register is set, the bclxif bit of the pirx register is set. once a bus collision is detected, the slave goes idle and waits to be addressed again. user software can use the bclxif bit to handle a slave bus collision. 21.5.3.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 21-18 can be used as a reference to this list. 1. master sends a start condition on sdax and sclx. 2. s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting sspxif bit. 4. slave hardware generates an ack and sets sspxif. 5. sspxif bit is cleared by user. 6. software reads the received address from sspxbuf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into sspxbuf. 9. ckp bit is set releasing sclx, allowing the master to clock the data out of the slave. 10. sspxif is set after the ack response from the master is loaded into the ackstat register. 11. sspxif bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but sspxif is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of sclx (9th) rather than the falling. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 216 ? 2011-2015 microchip technology inc. figure 21-18: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sdax sclx sspxif bf ckp ackstat r/w d/a sp received address when r/w is set r/w is copied from the indicates an address is read from sspxbuf sclx is always held low after 9th sclx falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of sclx data to transmit is loaded into sspxbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 217 pic16(l)f1526/7 21.5.3.3 7-bit transmission with address hold enabled setting the ahen bit of the sspxcon3 register enables additional clock stretching and interrupt gen- eration after the 8th falling edge of a received match- ing address. once a matching address has been clocked in, ckp is cleared and the sspxif interrupt is set. figure 21-19 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the 8th falling edge of the sclx line the ckp bit is cleared and sspxif interrupt is gen- erated. 4. slave software clears sspxif. 5. slave software reads acktim bit of sspxcon3 register, and r/w and d/a of the sspxstat register to determine the source of the interrupt. 6. slave reads the address value from the sspxbuf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets the ackdt bit of the sspxcon2 register accordingly. 8. slave sets the ckp bit releasing sclx. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets sspxif after the ack if the r/w bit is set. 11. slave software clears sspxif. 12. slave loads value to transmit to the master into sspxbuf setting the bf bit. 13. slave sets ckp bit releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the 9th sclx pulse. 15. slave hardware copies the ack value into the ackstat bit of the sspxcon2 register. 16. steps 10-15 are repeated for each byte transmit- ted to the master from the slave. 17. if the master sends a not ack the slave releases the bus allowing the master to send a stop and end the communication. note: sspxbuf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the sclx line to receive a stop. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 218 ? 2011-2015 microchip technology inc. figure 21-19: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sdax sclx sspxif bf ackdt ackstat ckp r/w d/a received address is read from sspxbuf bf is automatically cleared after 8th falling edge of sclx data to transmit is loaded into sspxbuf cleared by software slave clears ackdt to ack address masters ack response is copied to sspxstat ckp not cleared after not ack set by software, releases sclx acktim is cleared on 9th rising edge of sclx acktim is set on 8th falling edge of sclx when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sdax to slave for ack sequence ack ack acktim downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 219 pic16(l)f1526/7 21.5.4 slave mode 10-bit address reception this section describes a standard sequence of events for the msspx module configured as an i 2 c slave in 10-bit addressing mode. figure 21-20 is used as a visual reference for this description. this is a step by step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the sspxstat register is set. 4. slave sends ack and sspxif is set. 5. software clears the sspxif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. slave loads low address into sspxadd, releasing sclx. 8. master sends matching low address byte to the slave; ua bit is set. 9. slave sends ack and sspxif is set. 10. slave clears sspxif. 11. slave reads the received matching address from sspxbuf clearing bf. 12. slave loads high address into sspxadd. 13. master clocks a data byte to the slave and clocks out the slaves ack on the 9th sclx pulse; sspxif is set. 14. if sen bit of sspxcon2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears sspxif. 16. slave reads the received byte from sspxbuf clearing bf. 17. if sen is set the slave sets ckp to release the sclx. 18. steps 13-17 repeat for each received byte. 19. master sends stop to end the transmission. 21.5.5 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the sspxadd register using the ua bit. all functionality, specifically when the ckp bit is cleared and sclx line is held low are the same. figure 21-21 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 21-22 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the sspxadd register are not allowed until after the ack sequence. note: if the low address does not match, sspxif and ua are still set so that the slave soft- ware can set sspxadd back to the high address. bf is not set because there is no match. ckp is unaffected. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 220 ? 2011-2015 microchip technology inc. figure 21-20: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sspxif receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx ua ckp 1 2345678 912345678 912345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates sspxadd data is read sclx is held low set by software, while ckp = 0 from sspxbuf releasing sclx when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from sspxbuf and releases sclx when ua = 1 ; if address matches set by hardware on 9th falling edge sspxadd it is loaded into sspxbuf sclx is held low s bf downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 221 pic16(l)f1526/7 figure 21-21: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sdax sclx sspxif bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 sspxbuf is read from received data sspxbuf can be read anytime before the next received byte cleared by software falling edge of sclx not allowed until 9th update to sspxadd is set ckp with software releases sclx sclx clears ua and releases update of sspxadd, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of sclx of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of sclx cleared by software r/w = 0 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 222 ? 2011-2015 microchip technology inc. figure 21-22: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx sspxif bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 23 4 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after sspxadd is updated, ua is cleared and sclx is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates sspxadd sspxbuf loaded with received address must be updated has been received loaded into sspxbuf releases sclx masters not ack is copied matching address byte ckp is cleared on 9th falling edge of sclx read from sspxbuf back into sspxadd ackstat set by hardware downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 223 pic16(l)f1526/7 21.5.6 clock stretching clock stretching occurs when a device on the bus holds the sclx line low effectively pausing communi- cation. the slave may stretch the clock to allow more time to handle data or prepare a response for the mas- ter device. a master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. any stretching done by a slave is invisible to the master software and han- dled by the hardware that generates sclx. the ckp bit of the sspxcon1 register is used to con- trol stretching in software. any time the ckp bit is cleared, the module will wait for the sclx line to go low and then hold it. setting ckp will release sclx and allow more communication. 21.5.6.1 normal clock stretching following an ack if the r/w bit of sspxstat is set, a read request, the slave hardware will clear ckp. this allows the slave time to update sspxbuf with data to transfer to the master. if the sen bit of sspxcon2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready; ckp is set by software and communication resumes. 21.5.6.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set, the clock is always stretched. this is the only time the sclx is stretched without ckp being cleared. sclx is released immediately after a write to sspxadd. 21.5.6.3 byte nacking when ahen bit of sspxcon3 is set; ckp is cleared by hardware after the 8th falling edge of sclx for a received matching address byte. when dhen bit of sspxcon3 is set; ckp is cleared after the 8th falling edge of sclx for received data. stretching after the 8th falling edge of sclx allows the slave to look at the received address or data and decide if it wants to ack the received data. 21.5.7 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the sclx line to go low and then hold it. however, clearing the ckp bit will not assert the sclx output low until the sclx output is already sampled low. therefore, the ckp bit will not assert the sclx line until an external i 2 c master device has already asserted the sclx line. the sclx output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released sclx. this ensures that a write to the ckp bit will not violate the minimum high time requirement for sclx (see figure 21-23 ). figure 21-23: clock synchronization timing note 1: the bf bit has no effect on if the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock, clear ckp, if sspxbuf was read before the 9th falling edge of sclx. 2: previous versions of the module did not stretch the clock for a transmission if sspxbuf was loaded before the 9th fall- ing edge of sclx. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sdax sclx dx ? C 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspxcon1 ckp master device releases clock master device asserts clock downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 224 ? 2011-2015 microchip technology inc. 21.5.8 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master device. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the sspxcon2 register is set, the slave module will automatically ack the reception of this address regardless of the value stored in sspxadd. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave software can read sspxbuf and respond. figure 21-24 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in 7-bit mode. if the ahen bit of the sspxcon3 register is set, just as with any other address reception, the slave hard- ware will stretch the clock after the 8th falling edge of sclx. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 21-24: slave mode general call address sequence 21.5.9 sspx mask register an sspx mask (sspxmsk) register ( register 21-5 ) is available in i 2 c slave mode as a mask for the value held in the sspxsr register during an address comparison operation. a zero ( 0 ) bit in the sspxmsk register has the effect of making the corresponding bit of the received address a dont care. this register is reset to all 1 s upon any reset condition and, therefore, has no effect on standard sspx operation until written with a mask value. the sspx mask register is active during: 7-bit address mode: address compare of a<7:1>. 10-bit address mode: address compare of a<7:0> only. the sspx mask has no effect during the reception of the first (high) byte of the address. sdax sclx s sspxif bf (sspxstat<0>) cleared by software sspxbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspxcon2<7>) 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 225 pic16(l)f1526/7 21.6 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspm bits in the sspxcon1 register and by setting the sspen bit. in master mode, the sda and sck pins must be configured as inputs. the mssp peripheral hardware will override the output driver tris controls when necessary to drive the pins low. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the msspx module is disabled. con- trol of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sdax and sclx lines. the following events will cause the sspx interrupt flag bit, sspxif, to be set (sspx interrupt, if enabled): start condition detected stop condition detected data transfer byte transmitted/received acknowledge transmitted/received repeated start generated 21.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sdax, while sclx outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic 0 . serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic 1 . thus, the first byte transmitted is a 7-bit slave address followed by a 1 to indicate the receive bit. serial data is received via sdax, while sclx outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. a baud rate generator is used to set the clock frequency output on sclx. see section 21.7 ?baud rate generator? for more detail. note 1: the msspx module, when configured in i 2 c master mode, does not allow queue- ing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspxbuf register to initiate transmission before the start condition is complete. in this case, the sspxbuf will not be written to and the wcol bit will be set, indicating that a write to the sspxbuf did not occur 2: when in master mode, start/stop detec- tion is masked and an interrupt is gener- ated when the sen/pen bit is cleared and the generation is complete. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 226 ? 2011-2015 microchip technology inc. 21.6.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the sclx pin (sclx allowed to float high). when the sclx pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the sclx pin is actually sampled high. when the sclx pin is sampled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and begins counting. this ensures that the sclx high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 21-25 ). figure 21-25: baud rate generator timing with clock arbitration 21.6.3 wcol status flag if the user writes the sspxbuf when a start, restart, stop, receive or transmit sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set it indicates that an action on sspxbuf was attempted while the module was not idle. sdax sclx sclx deasserted but slave holds dx ? C 1 dx brg sclx is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value sclx low (clock arbitration) sclx allowed to transition high brg decrements on q2 and q4 cycles note: because queueing of events is not allowed, writing to the lower 5 bits of sspxcon2 is disabled until the start condition is complete. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 227 pic16(l)f1526/7 21.6.4 i 2 c master mode start condition timing to initiate a start condition ( figure 21-26 ), the user sets the start enable bit, sen bit of the sspxcon2 register. if the sdax and sclx pins are sampled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and starts its count. if sclx and sdax are both sampled high when the baud rate generator times out (t brg ), the sdax pin is driven low. the action of the sdax being driven low while sclx is high is the start condition and causes the s bit of the sspxstat1 register to be set. following this, the baud rate generator is reloaded with the contents of sspxadd<7:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit of the sspxcon2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sdax line held low and the start condition is complete. figure 21-26: first start bit timing note 1: if at the beginning of the start condition, the sdax and sclx pins are already sam- pled low, or if during the start condition, the sclx line is sampled low before the sdax line is driven low, a bus collision occurs, the bus collision interrupt flag, bclxif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c specification states that a bus collision cannot occur on a start. sdax sclx s t brg 1st bit 2nd bit t brg sdax = 1 , at completion of start bit, sclx = 1 write to sspxbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspxstat<3>) and sets sspxif bit downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 228 ? 2011-2015 microchip technology inc. 21.6.5 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit of the sspxcon2 register is programmed high and the master state machine is no longer active. when the rsen bit is set, the sclx pin is asserted low. when the sclx pin is sampled low, the baud rate generator is loaded and begins counting. the sdax pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sdax is sampled high, the sclx pin will be deasserted (brought high). when sclx is sampled high, the baud rate generator is reloaded and begins counting. sdax and sclx must be sampled high for one t brg . this action is then followed by assertion of the sdax pin (sdax = 0 ) for one t brg while sclx is high. sclx is asserted low. following this, the rsen bit of the sspx- con2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sdax pin held low. as soon as a start condition is detected on the sdax and sclx pins, the s bit of the sspxstat register will be set. the sspxif bit will not be set until the baud rate generator has timed out. figure 21-27: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sdax is sampled low when sclx goes from low-to-high. sclx goes low before sdax is asserted low. this may indicate that another master is attempting to transmit a data 1 . sdax sclx repeated start write to sspxcon2 write to sspxbuf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sdax = 1 , sdax = 1 , sclx (no change) sclx = 1 occurs here t brg t brg t brg and sets sspxif sr downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 229 pic16(l)f1526/7 21.6.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspxbuf register. this action will set the buffer full flag bit, bf and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sdax pin after the falling edge of sclx is asserted. sclx is held low for one baud rate genera- tor rollover count (t brg ). data should be valid before sclx is released high. when the sclx pin is released high, it is held that way for t brg . the data on the sdax pin must remain stable for that duration and some hold time after the next falling edge of sclx. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sdax. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackstat bit on the rising edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspxif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspxbuf, leaving sclx low and sdax unchanged ( figure 21-28 ). after the write to the sspxbuf, each bit of the address will be shifted out on the falling edge of sclx until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will release the sdax pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sdax pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the sspxcon2 register. following the falling edge of the ninth clock transmission of the address, the sspxif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspxbuf takes place, holding sclx low and allowing sdax to float. 21.6.6.1 bf status flag in transmit mode, the bf bit of the sspxstat register is set when the cpu writes to sspxbuf and is cleared when all 8 bits are shifted out. 21.6.6.2 wcol status flag if the user writes the sspxbuf when a transmit is already in progress (i.e., sspxsr is still shifting out a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 21.6.6.3 ackstat status flag in transmit mode, the ackstat bit of the sspxcon2 register is cleared when the slave has sent an acknowl- edge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowl- edge when it has recognized its address (including a general call), or when the slave has properly received its data. 21.6.6.4 typical transmit sequence: 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspxif is set by hardware on completion of the start. 3. sspxif is cleared by software. 4. the msspx module will wait the required start time before any other operation takes place. 5. the user loads the sspxbuf with the slave address to transmit. 6. address is shifted out the sdax pin until all 8 bits are transmitted. transmission begins as soon as sspxbuf is written to. 7. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 8. the msspx module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 9. the user loads the sspxbuf with eight bits of data. 10. data is shifted out the sdax pin until all 8 bits are transmitted. 11. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 12. steps 8-11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the sspx- con2 register. interrupt is generated once the stop/restart condition is complete. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 230 ? 2011-2015 microchip technology inc. figure 21-28: i 2 c master mode waveform (transmission, 7 or 10-bit address) sdax sclx sspxif bf (sspxstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine sspxbuf is written by software from sspx interrupt after start condition, sen cleared by hardware s sspxbuf written with 7-bit address and r/w start transmit sclx held low while cpu responds to sspxif sen = 0 of 10-bit address write sspxcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspxcon2<6> ackstat in sspxcon2 = 1 cleared by software sspxbuf written pen r/w cleared by software downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 231 pic16(l)f1526/7 21.6.7 i 2 c master mode reception master mode reception ( figure 21-29 ) is enabled by programming the receive enable bit, rcen bit of the sspxcon2 register. the baud rate generator begins counting and on each rollover, the state of the sclx pin changes (high-to-low/low-to-high) and data is shifted into the sspxsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the sspxsr are loaded into the sspxbuf, the bf flag bit is set, the sspxif flag bit is set and the baud rate generator is suspended from counting, holding sclx low. the msspx is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable, acken bit of the sspxcon2 register. 21.6.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspxbuf from sspxsr. it is cleared when the sspxbuf register is read. 21.6.7.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspxsr and the bf flag bit is already set from a previous reception. 21.6.7.3 wcol status flag if the user writes the sspxbuf when a receive is already in progress (i.e., sspxsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 21.6.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspxif is set by hardware on completion of the start. 3. sspxif is cleared by software. 4. user writes sspxbuf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sdax pin until all 8 bits are transmitted. transmission begins as soon as sspxbuf is written to. 6. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 7. the msspx module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 8. user sets the rcen bit of the sspxcon2 regis- ter and the master clocks in a byte from the slave. 9. after the 8th falling edge of sclx, sspxif and bf are set. 10. master clears sspxif and reads the received byte from sspxuf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the sspxcon2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and sspxif is set. 13. user clears sspxif. 14. steps 8-13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the msspx module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 232 ? 2011-2015 microchip technology inc. figure 21-29: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sdax sclx 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w transmit address to slave sspxif bf ack is not sent write to sspxcon2<0>(sen = 1 ), write to sspxbuf occurs here, ack from slave master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 sspov sdax = 0 , sclx = 1 while cpu (sspxstat<0>) ack cleared by software cleared by software set sspxif interrupt at end of receive set p bit (sspxstat<4>) and sspxif cleared in software ack from master set sspxif at end set sspxif interrupt at end of acknowledge sequence set sspxif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspxbuf is still full sdax = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspxcon2<4> to start acknowledge sequence sdax = ackdt (sspxcon2<5>) = 0 rcen cleared automatically responds to sspxif acken begin start condition cleared by software sdax = ackdt = 0 last bit is shifted into sspxsr and contents are unloaded into sspxbuf rcen master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) rcen cleared automatically ack from master sdax = ackdt = 0 rcen cleared automatically downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 233 pic16(l)f1526/7 21.6.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken bit of the sspxcon2 register. when this bit is set, the sclx pin is pulled low and the contents of the acknowledge data bit are presented on the sdax pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the sclx pin is deasserted (pulled high). when the sclx pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the sclx pin is then pulled low. following this, the acken bit is auto- matically cleared, the baud rate generator is turned off and the msspx module then goes into idle mode ( figure 21-30 ). 21.6.8.1 wcol status flag if the user writes the sspxbuf when an acknowledge sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 21.6.9 stop condition timing a stop bit is asserted on the sdax pin at the end of a receive/transmit by setting the stop sequence enable bit, pen bit of the sspxcon2 register. at the end of a receive/transmit, the sclx line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sdax line low. when the sdax line is sampled low, the baud rate generator is reloaded and counts down to 0 . when the baud rate generator times out, the sclx pin will be brought high and one t brg (baud rate generator rollover count) later, the sdax pin will be deasserted. when the sdax pin is sampled high while sclx is high, the p bit of the sspxstat register is set. a t brg later, the pen bit is cleared and the sspxif bit is set ( figure 21-31 ). 21.6.9.1 wcol status flag if the user writes the sspxbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 21-30: acknowledge sequen ce waveform note: t brg = one baud rate generator period. sdax sclx sspxif set at acknowledge sequence starts here, write to sspxcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspxif software sspxif set at the end of acknowledge sequence cleared in software ack downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 234 ? 2011-2015 microchip technology inc. figure 21-31: stop cond ition receive or transmit mode 21.6.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the msspx interrupt is enabled). 21.6.11 effects of a reset a reset disables the msspx module and terminates the current transfer. 21.6.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the msspx module is disabled. control of the i 2 c bus may be taken when the p bit of the sspxstat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the sspx interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sdax line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bclxif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 21.6.13 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sdax pin, arbitration takes place when the master outputs a 1 on sdax, by letting sdax float high and another master asserts a 0 . when the sclx pin floats high, data should be stable. if the expected data on sdax is a 1 and the data sampled on the sdax pin is 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclxif and reset the i 2 c port to its idle state ( figure 21-32 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sdax and sclx lines are deasserted and the sspxbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sdax and sclx lines are deasserted and the respective control bits in the sspxcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. the master will continue to monitor the sdax and sclx pins. if a stop condition occurs, the sspxif bit will be set. a write to the sspxbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspxstat register, or the bus is idle and the s and p bits are cleared. sclx sdax sdax asserted low before rising edge of clock write to sspxcon2, set pen falling edge of sclx = 1 for t brg , followed by sdax = 1 for t brg 9th clock sclx brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sdax sampled high. p bit (sspxstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspxcon2<2>) is cleared by hardware and the sspxif bit is set downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 235 pic16(l)f1526/7 figure 21-32: bus collision timing for transmit and acknowledge sdax sclx bclxif sdax released sdax line pulled low by another source sample sdax. while sclx is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bclxif) by the master. by master data changes while sclx = 0 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 236 ? 2011-2015 microchip technology inc. 21.6.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sdax or sclx are sampled low at the beginning of the start condition ( figure 21-33 ). b) sclx is sampled low before sdax is asserted low ( figure 21-34 ). during a start condition, both the sdax and the sclx pins are monitored. if the sdax pin is already low, or the sclx pin is already low, then all of the following occur: the start condition is aborted, the bclxif flag is set and the msspx module is reset to its idle state ( figure 21-33 ). the start condition begins with the sdax and sclx pins deasserted. when the sdax pin is sampled high, the baud rate generator is loaded and counts down. if the sclx pin is sampled low while sdax is high, a bus collision occurs because it is assumed that another master is attempting to drive a data 1 during the start condition. if the sdax pin is sampled low during this count, the brg is reset and the sdax line is asserted early ( figure 21-35 ). if, however, a 1 is sampled on the sdax pin, the sdax pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the sclx pin is sampled as 0 during this time, a bus collision does not occur. at the end of the brg count, the sclx pin is asserted low. figure 21-33: bus collision during st art condition (sdax only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. there- fore, one master will always assert sdax before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sdax sclx sen sdax sampled low before sdax goes low before the sen bit is set. s bit and sspxif set because sspx module reset into idle state. sen cleared automatically because of bus collision. s bit and sspxif set because set sen, enable start condition if sdax = 1 , sclx = 1 sdax = 0 , sclx = 1 . bclxif s sspxif sdax = 0 , sclx = 1 . sspxif and bclxif are cleared by software sspxif and bclxif are cleared by software set bclxif, start condition. set bclxif. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 237 pic16(l)f1526/7 figure 21-34: bus collision d uring start condition (sclx = 0 ) figure 21-35: brg reset due to sda arbitration during start condition sdax sclx sen bus collision occurs. set bclxif. sclx = 0 before sdax = 0 , set sen, enable start sequence if sdax = 1 , sclx = 1 t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif interrupt cleared by software bus collision occurs. set bclxif. sclx = 0 before brg time-out, 0 0 0 0 sdax sclx sen set s less than t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif s interrupts cleared by software set sspxif sdax = 0 , sclx = 1 , sclx pulled low after brg time-out set sspxif 0 sdax pulled low by other master. reset brg and assert sdax. set sen, enable start sequence if sdax = 1 , sclx = 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 238 ? 2011-2015 microchip technology inc. 21.6.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sdax when sclx goes from low level to high level (case 1). b) sclx goes low before sdax is asserted low, indicating that another master is attempting to transmit a data 1 (case 2). when the user releases sdax and the pin is allowed to float high, the brg is loaded with sspxadd and counts down to zero. the sclx pin is then deasserted and when sampled high, the sdax pin is sampled. if sdax is low, a bus collision has occurred (i.e., another master is attempting to transmit a data 0 , figure 21-36 ). if sdax is sampled high, the brg is reloaded and begins counting. if sdax goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sdax at exactly the same time. if sclx goes from high-to-low before the brg times out and sdax has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data 1 during the repeated start condition, see figure 21-37 . if, at the end of the brg time-out, both sclx and sdax are still high, the sdax pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the sclx pin, the sclx pin is driven low and the repeated start condition is complete. figure 21-36: bus collision during a repeat ed start condition (case 1) figure 21-37: bus collision during repeated start condition (case 2) sdax sclx rsen bclxif s sspxif sample sdax when sclx goes high. if sdax = 0 , set bclxif and release sdax and sclx. cleared by software 0 0 sdax sclx bclxif rsen s sspxif interrupt cleared by software sclx goes low before sdax, set bclxif. release sdax and sclx. t brg t brg 0 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 239 pic16(l)f1526/7 21.6.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sdax pin has been deasserted and allowed to float high, sdax is sampled low after the brg has timed out (case 1). b) after the sclx pin is deasserted, sclx is sampled low before sdax goes high (case 2). the stop condition begins with sdax asserted low. when sdax is sampled low, the sclx pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspxadd and counts down to 0. after the brg times out, sdax is sampled. if sdax is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data 0 ( figure 21-38 ). if the sclx pin is sampled low before sdax is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data 0 ( figure 21-39 ). figure 21-38: bus collision during a stop condition (case 1) figure 21-39: bus collision during a stop condition (case 2) sdax sclx bclxif pen p sspxif t brg t brg t brg sdax asserted low sdax sampled low after t brg , set bclxif 0 0 sdax sclx bclxif pen p sspxif t brg t brg t brg assert sdax sclx goes low before sdax goes high, set bclxif 0 0 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 240 ? 2011-2015 microchip technology inc. table 21-3: summary of registers associated with i 2 c operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page: intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie2 osfie tmr5gie tmr3gie bcl1ie tmr10ie tmr8ie ccp2ie 78 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir2 osfif tmr5gif tmr3gif bcl1if tmr10if tmr8if ccp2if 82 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 ssp1add add<7:0> 247 ssp2add add<7:0> 247 ssp1buf msspx receive buffer/transmit register 197* ssp2buf msspx receive buffer/transmit register 197* ssp1con1 wcol sspov sspen ckp sspm<3:0> 244 ssp2con1 wcol sspov sspen ckp sspm<3:0> 244 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 245 ssp2con2 gcen ackstat ackdt acken rcen pen rsen sen 245 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 246 ssp2con3 acktim pcie scie boen sdaht sbcde ahen dhen 246 ssp1msk msk<7:0> 247 ssp2msk msk<7:0> 247 ssp1stat smp cke d/a psr / w ua bf 242 ssp2stat smp cke d/a psr / w ua bf 242 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 123 legend: = unimplemented location, read as 0 . shaded cells are not used by the mssp module in i 2 c mode. * page provides register information. note 1: pic16(l)f1527 only. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 241 pic16(l)f1526/7 21.7 baud rate generator the msspx module has a baud rate generator avail- able for clock generation in both i 2 c and spi master modes. the baud rate generator (brg) reload value is placed in the sspxadd register ( register 21-6 ). when a write occurs to sspxbuf, the baud rate generator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal reload in figure 21-40 triggers the value from sspxadd to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the msspx is being operated in. table 21-4 demonstrates clock rates based on instruction cycles and the brg value loaded into sspxadd. equation 21-1: figure 21-40: baud rate genera tor block diagram table 21-4: msspx clock rate w/brg f clock f osc sspxadd 1 + ?? 4 ?? ------------------------------------------------- = note: values of 0x00, 0x01 and 0x02 are not valid for sspxadd when used as a baud rate generator for i 2 c. this is an implementation limitation. f osc f cy brg value f clock (2 rollovers of brg) 16 mhz 4 mhz 09h 400 khz (1) 16 mhz 4 mhz 0ch 308 khz 16 mhz 4 mhz 27h 100 khz 4 mhz 1 mhz 09h 100 khz note 1: refer to i/o port electrical and timing specifications in tab l e 2 5- 3 and figure 25-7 to ensure the system is designed to support the i/o timing requirements. sspm<3:0> brg down counter sspxclk f osc /2 sspxadd<7:0> sspm<3:0> sclx reload control reload downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 242 ? 2011-2015 microchip technology inc. 21.8 register definitions: mssp control register 21-1: sspxstat: sspx status register r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 smp cke d/a psr / w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 smp: spi data input sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select bit (spi mode only) in spi master or slave mode: 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state in i 2 c ? mode only: 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the msspx module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is 0 on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the msspx module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is 0 on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the msspx is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspxadd register 0 = address does not need to be updated downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 243 pic16(l)f1526/7 bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspxbuf is full 0 = receive not complete, sspxbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspxbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspxbuf is empty register 21-1: sspxstat: sspx status register (continued) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 244 ? 2011-2015 microchip technology inc. register 21-2: sspxcon1: ss px control register 1 r/c/hs-0/0 r/c/hs-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wcol sspxov sspen ckp sspm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = bit is set by hardware c = user cleared bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspxbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspxbuf register is written while it is still transmitting the previous wor d (must be cleared in software) 0 = no collision bit 6 sspxov: receive overflow indicator bit (1) in spi mode: 1 = a new byte is received while the sspxbuf register is still holding the pr evious data. in case of overflow, the data in sspxsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspxbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (an d transmission) is initiated by writi ng to the sspxbuf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspxbuf register is still holding the previous b yte. sspxov is a dont care in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output in spi mode: 1 = enables serial port and configures sckx, sdox, sdix and ssx as the source of the serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sdax and sclx pins as the source of the serial port pins (3) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: sclx release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3-0 sspm<3:0>: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1101 = reserved 1100 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1010 = spi master mode, clock = f osc /(4 * (sspxadd+1)) (5) 1001 = reserved 1000 = i 2 c master mode, clock = f osc /(4 * (sspxadd+1)) (4) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address 0101 = spi slave mode, clock = sckx pin, ssx pin control disabled, ssx can be used as i/o pin 0100 = spi slave mode, clock = sckx pin, ssx pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note 1: in master mode, the overflow bit is not set since each new reception (and transmis sion) is initiated by writing to the sspxbuf register. 2: when enabled, these pins must be properly configured as input or output. 3: when enabled, the sdax and sclx pins must be configured as inputs. 4: sspxadd values of 0, 1 or 2 are not supported for i 2 c mode. 5: sspxadd value of 0 is not supported. use sspm = 0000 instead. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 245 pic16(l)f1526/7 register 21-3: sspxcon2: ss px control register 2 r/w-0/0 r-0/0 r/w-0/0 r/s/hs-0/0 r/s/hs- 0/0 r/s/hs-0/0 r/s/hs-0/0 r/w/hs-0/0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hc = cleared by hardware s = user set bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the sspxsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sdax and sclx pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sckx release control: 1 = initiate stop condition on sdax and sclx pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sdax and sclx pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit i n master mode: 1 = initiate start condition on sdax and sclx pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspxbuf may not be written (or writes to the sspxbuf are disabled). downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 246 ? 2011-2015 microchip technology inc. register 21-4: sspxcon3: ss px control register 3 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 acktim pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 acktim: acknowledge time status bit (i 2 c mode only) (3) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on 8 th falling edge of sclx clock 0 = not an acknowledge sequence, cleared on 9 th rising edge of sclx clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled (2) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled (2) bit 4 boen: buffer overwrite enable bit in spi slave mode: (1) 1 = sspxbuf updates every time that a new data byte is shifted in ignoring the bf bit 0 = if new byte is received with bf bit of the sspxstat register already set, sspov bit of the sspxcon1 register is set, and the buffer is not updated in i 2 c master mode and spi master mode: this bit is ignored. in i 2 c slave mode: 1 = sspxbuf is updated and ack is generated for a received address/data byte, ignoring the state of the sspov bit only if the bf bit = 0 . 0 = sspxbuf is only updated when sspov is clear bit 3 sdaht: sdax hold time selection bit (i 2 c mode only) 1 = minimum of 300 ns hold time on sdax after the falling edge of sclx 0 = minimum of 100 ns hold time on sdax after the falling edge of sclx bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if on the rising edge of sclx, sdax is sampled low when the module is outputting a high state, the bclxif bit of the pir2 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of sclx for a matching received address byte; ckp bit of the sspxcon1 register will be cleared and the sclx will be held low. 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of sclx for a received data byte; slave hardware clears the ckp bit of the sspxcon1 register and sclx is held low. 0 = data holding is disabled note 1: for daisy-chained spi operation; allows the user to igno re all but the last received byte. sspov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to sspxbuf. 2: this bit has no effect in slave modes that start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is only active when the ahen bit or dhen bit is set. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 247 pic16(l)f1526/7 register 21-5: sspxmsk: sspx mask register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 msk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to sspxadd to detect i 2 c address match 0 = the received address bit n is not used to detect i 2 c address match bit 0 msk<0>: mask bit for i 2 c slave mode, 10-bit address i 2 c slave mode, 10-bit address (sspm<3:0> = 0111 or 1111 ): 1 = the received address bit 0 is compared to sspxadd<0> to detect i 2 c address match 0 = the received address bit 0 is not used to detect i 2 c address match i 2 c slave mode, 7-bit address, the bit is ignored register 21-6: sspxadd: msspx address and baud rate register (i 2 c mode) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 add<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared master mode: bit 7-0 add<7:0>: baud rate clock divider bits sclx pin clock period = ((add<7:0> + 1) *4)/f osc 10-bit slave mode ? most significant address byte: bit 7-3 not used: unused for most significant address byte. bit state of this register is a dont care. bit pat- tern sent by master is fixed by i 2 c specification and must be equal to 11110 . however, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 add<2:1>: two most significant bits of 10-bit address bit 0 not used: unused in this mode. bit state is a dont care. 10-bit slave mode ? least significant address byte: bit 7-0 add<7:0>: eight least significant bits of 10-bit address 7-bit slave mode: bit 7-1 add<7:1>: 7-bit address bit 0 not used: unused in this mode. bit state is a dont care. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 248 ? 2011-2015 microchip technology inc. 22.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the eusart, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the eusart module includes the following capabilities: full-duplex asynchronous transmit and receive two-character input buffer one-character output buffer programmable 8-bit or 9-bit character length address detection in 9-bit mode input buffer overrun error detection received character framing error detection half-duplex synchronous master half-duplex synchronous slave programmable clock and data polarity the eusart module implements the following additional features, making it ideally suited for use in local interconnect network (lin) bus systems: automatic detection and calibration of the baud rate wake-up on break reception 13-bit break character transmit block diagrams of the eusart transmitter and receiver are shown in figure 22-1 and figure 22-2 . figure 22-1: eusart transmi t block diagram note: the pic16(l)f1526/7 devices have two eusarts. therefore, all information in this section refers to both eusart 1 and eusart 2. txxif txxie interrupt txen tx9d msb lsb data bus txxreg register transmit shift register (tsr) (8) 0 tx9 trmt txx/ckx pin pin buffer and control 8 spxbrgl spxbrgh brg16 f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 249 pic16(l)f1526/7 figure 22-2: eusart receiv e block diagram the operation of the eusart module is controlled through three registers: transmit status and control (txxsta) receive status and control (rcxsta) baud rate control (baudxcon) these registers are detailed in register 22-1 , register 22-2 and register 22-3 , respectively. for all modes of eusart operation, the tris control bits corresponding to the rxx/dtx and txx/ckx pins should be set to 1 . the eusart control will automatically reconfigure the pin from input to output, as needed. when the receiver or transmitter section is not enabled then the corresponding rxx/dtx or txx/ckx pin may be used for general purpose input and output. rxx/dtx pin pin buffer and control data recovery cren oerr ferr rsr register msb lsb rx9d rcxreg register fifo interrupt rcxif rcxie data bus 8 stop start (8) 7 1 0 rx9 spxbrgl spxbrgh brg16 rcidl f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 250 ? 2011-2015 microchip technology inc. 22.1 eusart asynchronous mode the eusart transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a 1 data bit, and a v ol space state which represents a 0 data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is 8 bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit/16-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. see table 22-5 for examples of baud rate configurations. the eusart transmits and receives the lsb first. the eusarts transmitter and receiver are functionally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 22.1.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 22-1 . the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the txxreg register. 22.1.1.1 enabling the transmitter the eusart transmitter is enabled for asynchronous operations by configuring the following three control bits: txen = 1 sync = 0 spen = 1 all other eusart control bits are assumed to be in their default state. setting the txen bit of the txxsta register enables the transmitter circuitry of the eusart. clearing the sync bit of the txxsta register configures the eusart for asynchronous operation. setting the spen bit of the rcxsta register enables the eusart. the program- mer must set the corresponding tris bit to configure the txx/ckx i/o pin as an output. if the txx/ckx pin is shared with an analog peripheral, the analog i/o function must be disabled by clearing the corresponding ansel bit. 22.1.1.2 transmitting data a transmission is initiated by writing a character to the txxreg register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txxreg is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the txxreg until the stop bit of the previous character has been transmitted. the pending character in the txxreg is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the txxreg. 22.1.1.3 transmit data polarity the polarity of the transmit data can be controlled with the sckp bit of the baudxcon register. the default state of this bit is 0 which selects high true transmit idle and data bits. setting the sckp bit to 1 will invert the transmit data resulting in low true idle and data bits. the sckp bit controls transmit data polarity only in asynchronous mode. in synchronous mode the sckp bit has a different function. 22.1.1.4 transmit interrupt flag the txxif interrupt flag bit of the pir1/pir4 register is set whenever the eusart transmitter is enabled and no character is being held for transmission in the txxreg. in other words, the txxif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the txxreg. the txxif flag bit is not cleared immediately upon writing txxreg. txxif becomes valid in the second instruction cycle following the write execution. polling txxif immediately following the txxreg write will return invalid results. the txxif bit is read-only, it cannot be set or cleared by software. the txxif interrupt can be enabled by setting the txxie interrupt enable bit of the pie1/pie4 register. however, the txxif flag bit will be set whenever the txxreg is empty, regardless of the state of txxie enable bit. to use interrupts when transmitting data, set the txxie bit only when there is more data to send. clear the txxie interrupt enable bit upon writing the last character of the transmission to the txxreg. note: the txxif transmitter interrupt flag is set when the txen enable bit is set. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 251 pic16(l)f1526/7 22.1.1.5 tsr status the trmt bit of the txxsta register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the txxreg. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user needs to poll this bit to determine the tsr status. 22.1.1.6 transmitting 9-bit characters the eusart supports 9-bit character transmissions. when the tx9 bit of the txxsta register is set the eusart will shift 9 bits out for each character transmit- ted. the tx9d bit of the txxsta register is the ninth, and most significant, data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the 8 least significant bits into the txxreg. all nine bits of data will be transferred to the tsr shift register immediately after the txxreg is written. a special 9-bit address mode is available for use with multiple receivers. see section 22.1.2.7 ?address detection? for more information on the address mode. 22.1.1.7 asynchronous transmission set-up: 1. initialize the spxbrgh:spxbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. set the rxx/dtx and txx/ckx tris controls to 1 . 3. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 4. if 9-bit transmission is desired, set the tx9 control bit. a set ninth data bit will indicate that the 8 least significant data bits are an address when the receiver is set for address detection. 5. set the sckp control bit if inverted transmit data polarity is desired. 6. enable the transmission by setting the txen control bit. this will cause the txxif interrupt bit to be set. 7. if interrupts are desired, set the txxie interrupt enable bit. an interrupt will occur immediately provided that the gie and peie bits of the intcon register are also set. 8. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 9. load 8-bit data into the txxreg register. this will start the transmission. figure 22-3: asynchronous transmission note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txxreg word 1 brg output (shift clock) txx/ckx txxif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy pin downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 252 ? 2011-2015 microchip technology inc. figure 22-4: asynchronous transmiss ion (back-to-back) transmit shift reg write to txxreg brg output (shift clock) txx/ckx txxif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy pin table 22-1: summary of registers asso ciated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl sckp brg16 wue abden 260 baud2con abdovf rcidl sckp brg16 wue abden 260 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 80 rc1sta spen rx9 sren cren adden ferr oerr rx9d 259 rc2sta spen rx9 sren cren adden ferr oerr rx9d 259 sp1brgl eusart1 baud rate generator, low byte 261* sp1brgh eusart1 baud rate generator, high byte 261* sp2brgl eusart2 baud rate generator, low byte 261* sp2brgh eusart2 baud rate generator, high byte 261* tx1reg eusart1 transmit register 250* tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 258 tx2reg eusart2 transmit register 250* tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 258 legend: = unimplemented locations, read as 0 . shaded bits are not used for asynchronous transmission. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 253 pic16(l)f1526/7 22.1.2 eusart asynchronous receiver the asynchronous mode would typically be used in rs-232 systems. the receiver block diagram is shown in figure 22-2 . the data is received on the rxx/dtx pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character first-in-first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the eusart receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rcxreg register. 22.1.2.1 enabling the receiver the eusart receiver is enabled for asynchronous operation by configuring the following three control bits: cren = 1 sync = 0 spen = 1 all other eusart control bits are assumed to be in their default state. setting the cren bit of the rcxsta register enables the receiver circuitry of the eusart. clearing the sync bit of the txxsta register configures the eusart for asynchronous operation. setting the spen bit of the rcxsta register enables the eusart. the programmer must set the corresponding tris bit to configure the rxx/dtx i/o pin as an input. if the rxx/dtx pin is shared with an analog peripheral the analog i/o function must be disabled by clearing the corresponding ansel bit. 22.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting 0 or 1 is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a 1 . if the data recovery circuit samples a 0 in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. see section 22.1.2.4 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the eusart receive fifo and the rcxif interrupt flag bit of the pir1/pir4 register is set. the top charac- ter in the fifo is transferred out of the fifo by reading the rcxreg register. note 1: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. see section 22.1.2.5 ?receive overrun error? for more information on overrun errors. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 254 ? 2011-2015 microchip technology inc. 22.1.2.3 receive interrupts the rcxif interrupt flag bit of the pir1/pir4 register is set whenever the eusart receiver is enabled and there is an unread character in the receive fifo. the rcxif interrupt flag bit is read-only, it cannot be set or cleared by software. rcxif interrupts are enabled by setting the following bits: rcxie interrupt enable bit of the pie1/pie4 register peie peripheral interrupt enable bit of the intcon register gie global interrupt enable bit of the intcon register the rcxif interrupt flag bit will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. 22.1.2.4 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rcxsta register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rcxreg. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rcxsta register which resets the eusart. clearing the cren bit of the rcxsta register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 22.1.2.5 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rcxsta register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rcxsta register or by resetting the eusart by clearing the spen bit of the rcxsta register. 22.1.2.6 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcxsta register is set, the eusart will shift 9 bits into the rsr for each character received. the rx9d bit of the rcxsta register is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcxreg. 22.1.2.7 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rcxsta register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcxif interrupt bit. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rcxreg will not clear the ferr bit. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 255 pic16(l)f1526/7 22.1.2.8 asynchronous reception set-up: 1. initialize the spxbrgh:spxbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. set the rxx/dtx and txx/ckx tris controls to 1 . 3. enable the serial port by setting the spen bit and the rxx/dtx pin tris bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcxie interrupt enable bit and set the gie and peie bits of the intcon register. 5. if 9-bit reception is desired, set the rx9 bit. 6. enable reception by setting the cren bit. 7. the rcxif interrupt flag bit will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcxie interrupt enable bit was also set. 8. read the rcxsta register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. get the received 8 least significant data bits from the receive buffer by reading the rcxreg register. 10. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 22.1.2.9 9-bit address detection mode set-up this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spxbrgh, spxbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. set the rxx/dtx and txx/ckx tris controls to 1 . 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcxie interrupt enable bit and set the gie and peie bits of the intcon register. 5. enable 9-bit reception by setting the rx9 bit. 6. enable address detection by setting the adden bit. 7. enable reception by setting the cren bit. 8. the rcxif interrupt flag bit will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcxie interrupt enable bit was also set. 9. read the rcxsta register to get the error flags. the ninth data bit will always be set. 10. get the received 8 least significant data bits from the receive buffer by reading the rcxreg register. software determines if this is the devices address. 11. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 12. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts. figure 22-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rxx/dtx pin reg rcv buffer reg rcv shift read rcv buffer reg rcxreg rcxif (interrupt flag) oerr bit cren word 1 rcxreg word 2 rcxreg stop bit note: this timing diagram shows three words appearing on the rxx/dtx input. the rcxreg (recei ve buffer) is read after the third word, causing the oerr (overrun) bit to be set. rcidl downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 256 ? 2011-2015 microchip technology inc. table 22-2: summary of registers asso ciated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl sckp brg16 wue abden 260 baud2con abdovf rcidl sckp brg16 wue abden 260 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 rc1reg eusart1 receive register 253* rc1sta spen rx9 sren cren adden ferr oerr rx9d 259 rc2reg eusart2 receive register 253* rc2sta spen rx9 sren cren adden ferr oerr rx9d 259 sp1brgl eusart1 baud rate generator, low byte 261* sp1brgh eusart1 baud rate generator, high byte 261* sp2brgl eusart2 baud rate generator, low byte 261* sp2brgh eusart2 baud rate generator, high byte 261* trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 258 tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 258 legend: = unimplemented locations, read as 0 . shaded bits are not used for asynchronous reception. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 257 pic16(l)f1526/7 22.2 clock accuracy with asynchronous operation the factory calibrates the internal oscillator block output (hfintosc). however, the hfintosc frequency may drift as v dd or temperature changes, and this directly affects the asynchronous baud rate. the auto-baud detect feature (refer to section section 22.4.1, auto-baud detect ) can be used to compensate for changes in the intosc frequency. there may not be a fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency. the first (preferred) method uses the osctune register to adjust the hfintosc output. adjusting the value in the osctune register allows for fine resolution changes to the system clock source. see section 5.2 ?clock source types? for more information. the other method adjusts the value in the baud rate generator. this can be done automatically with the auto-baud detect feature (see section 22.4.1 ?auto-baud detect? ). there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 258 ? 2011-2015 microchip technology inc. 22.3 register definitions: eusart control register 22-1: txxsta: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode : dont care synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode : 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode : dont care bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 259 pic16(l)f1526/7 register 22-2: rcxsta: receiv e status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rxx/dtx and txx/ckx pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : dont care synchronous mode C master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode C slave dont care bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables receiver 0 = disables receiver synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : dont care bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcxreg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 260 ? 2011-2015 microchip technology inc. register 22-3: baudxcon: baud rate control register r-0/0 r-1/1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 abdovf rcidl sckp brg16 wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 abdovf: auto-baud detect overflow bit asynchronous mode : 1 = auto-baud timer overflowed 0 = auto-baud timer did not overflow synchronous mode : dont care bit 6 rcidl : receive idle flag bit asynchronous mode : 1 = receiver is idle 0 = start bit has been received and the receiver is receiving synchronous mode : dont care bit 5 unimplemented: read as 0 bit 4 sckp : synchronous clock polarity select bit asynchronous mode : 1 = transmit inverted data to the txx/ckx pin 0 = transmit non-inverted data to the txx/ckx pin synchronous mode : 1 = data is clocked on rising edge of the clock 0 = data is clocked on falling edge of the clock bit 3 brg16: 16-bit baud rate generator bit 1 = 16-bit baud rate generator is used 0 = 8-bit baud rate generator is used bit 2 unimplemented: read as 0 bit 1 wue: wake-up enable bit asynchronous mode : 1 = receiver is waiting for a falling edge. no character will be received, byte rcif wil l be set. wue will automatically clear after rcif is set. 0 = receiver is operating normally synchronous mode : dont care bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = auto-baud detect mode is enabled (clears when auto-baud is complete) 0 = auto-baud detect mode is disabled synchronous mode : dont care downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 261 pic16(l)f1526/7 22.4 eusart baud rate generator (brg) the baud rate generator (brg) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous eusart operation. by default, the brg operates in 8-bit mode. setting the brg16 bit of the baudxcon register selects 16-bit mode. the spxbrgh:spxbrgl register pair determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by both the brgh bit of the txxsta register and the brg16 bit of the baudxcon register. in synchronous mode, the brgh bit is ignored. example 22-1 provides a sample calculation for deter- mining the desired baud rate, actual baud rate, and baud rate % error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 22-5 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg (brg16 = 1 ) to reduce the baud rate error. the 16-bit brg mode is used to achieve slow baud rates for fast oscillator frequencies. writing a new value to the spxbrgh, spxbrgl register pair causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit to make sure that the receive operation is idle before changing the system clock. example 22-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: solving for spxbrgh:spxbrgl: spxbrgh: spxbrgl f osc desired baud rate --------------------------------------------- 64 --------------------------------------------- 1 ? = desired baud rate f osc 64 [spxbrgh:spxbrg] 1 + ?? ------------------------------------------------------------------------- - = 16000000 9600 ----------------------- - 64 ----------------------- -1 ? = 25.042 ?? 25 == actualbaudrate 16000000 64 25 1+ ?? -------------------------- - = 9615 = calc. baud rate desired baud rate ? desired baud rate -------------------------------------------------------------------------------------------- 9615 9600 ? ?? 9600 ---------------------------------- 0 . 1 6 % == baud rate % error = table 22-3: baud rate formulas configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n+1)] 001 8-bit/asynchronous f osc /[16 (n+1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n+1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = dont care, n = value of spxbrgh, spxbrgl register pair downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 262 ? 2011-2015 microchip technology inc. table 22-4: summary of registers asso ciated with the baud rate generator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page baud1con abdovf rcidl sckp brg16 wue abden 260 baud2con abdovf rcidl sckp brg16 wue abden 260 rc1sta spen rx9 sren cren adden ferr oerr rx9d 259 rc2sta spen rx9 sren cren adden ferr oerr rx9d 259 sp1brgl eusart1 baud rate generator, low byte 261* sp1brgh eusart1 baud rate generator, high byte 261* sp2brgl eusart2 baud rate generator, low byte 261* sp2brgh eusart2 baud rate generator, high byte 261* tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 258 tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 258 legend: = unimplemented, read as 0 . shaded bits are not used by the brg. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 263 pic16(l)f1526/7 table 22-5: baud rates for asynchronous modes baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 3 0 0 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k 57.60k 0.00 7 57.60k 0.00 2 115.2k baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 9600 9615 0.16 12 9600 0.00 5 10417 10417 0.00 11 10417 0.00 5 19.2k 19.20k 0.00 2 57.6k 57.60k 0.00 0 115.2k baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 1200 2400 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 264 ? 2011-2015 microchip technology inc. baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300 0.16 207 1200 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 57.6k 55556 -3.55 8 57.60k 0.00 3 115.2k 115.2k 0.00 1 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 57.6k 55556 -3.55 8 57.60k 0.00 3 115.2k 115.2k 0.00 1 table 22-5: baud rates for asynchronous modes (continued) downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 265 pic16(l)f1526/7 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 table 22-5: baud rates for asynchronous modes (continued) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 266 ? 2011-2015 microchip technology inc. 22.4.1 auto-baud detect the eusart module supports automatic detection and calibration of the baud rate. in the auto-baud detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rxx signal, the rxx signal is timing the brg. the baud rate generator is used to time the period of a received 55h (ascii u) which is the sync character for the lin bus. the unique feature of this character is that it has five rising edges including the stop bit edge. setting the abden bit of the baudxcon register starts the auto-baud calibration sequence ( figure 22.4.2 ). while the abd sequence takes place, the eusart state machine is held in idle. on the first rising edge of the receive line, after the start bit, the spxbrgl begins counting up using the brg counter clock as shown in tab l e 2 2- 6 . the fifth rising edge will occur on the rxx/dtx pin at the end of the eighth bit period. at that time, an accumulated value totaling the proper brg period is left in the spxbrgh:spxbrgl register pair, the abden bit is automatically cleared, and the rcxif interrupt flag is set. a read operation on the rcxreg needs to be performed to clear the rcxif interrupt. rcxreg content should be discarded. when calibrating for modes that do not use the spxbrgh register the user can verify that the spxbrgl register did not overflow by checking for 00h in the spxbrgh register. the brg auto-baud clock is determined by the brg16 and brgh bits as shown in table 22-6 . during abd, both the spxbrgh and spxbrgl registers are used as a 16-bit counter, independent of the brg16 bit set- ting. while calibrating the baud rate period, the spxbrgh and spxbrgl registers are clocked at 1/8th the brg base clock rate. the resulting byte mea- surement is the average bit time when clocked at full speed. figure 22-6: automatic baud rate calibration note 1: if the wue bit is set with the abden bit, auto-baud detection will occur on the byte following the break character (see section 22.4.3 ?auto-wake-up on break? ). 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible. 3: during the auto-baud process, the auto-baud counter starts counting at 1. upon completion of the auto-baud sequence, to achieve maximum accu- racy, subtract 1 from the spxbrgh:spxbrgl register pair. table 22-6: brg counter clock rates brg16 brgh brg base clock brg abd clock 00 f osc /64 f osc /512 01 f osc /16 f osc /128 10 f osc /16 f osc /128 11 f osc /4 f osc /32 note: during the abd sequence, spxbrgl and spxbrgh registers are both used as a 16-bit counter, independent of brg16 setting. brg value rxx/dtx pin abden bit rcxif bit bit 0 bit 1 (interrupt) read rcxreg brg clock start auto cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note 1: the abd sequence requires the eusart module to be configured in asynchronous mode. spxbrgl xxh 1ch spxbrgh xxh 00h rcidl downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 267 pic16(l)f1526/7 22.4.2 auto-baud overflow during the course of automatic baud detection, the abdovf bit of the baudxcon register will be set if the baud rate counter overflows before the fifth rising edge is detected on the rx pin. the abdovf bit indi- cates that the counter has exceeded the maximum count that can fit in the 16 bits of the spxbrgh:spxbrgl register pair. the overflow condi- tion will set the rcif flag. the counter continues to count until the fifth rising edge is detected on the rx pin. the rcidl bit will remain false ( 0 ) until the fifth rising edge at which time the rcidl bit will be set. if the rcreg is read after the overflow occurs but before the fifth rising edge, then the fifth rising edge will set the rcif again. terminating the auto-baud process early to clear an overflow condition will prevent proper detection of the sync character fifth rising edge. if any falling edges of the sync character have not yet occurred when the abden bit is cleared then those will be falsely detected as start bits. the following steps are recommended to clear the overflow condition: 1. read rcreg to clear rcif 2. if rcidl is zero then wait for rcif and repeat step 1. 3. clear the abdovf bit. 22.4.3 auto-wake-up on break during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper character reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rxx/dtx line. this feature is available only in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit of the baudxcon register. once set, the normal receive sequence on rxx/dtx is disabled, and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rxx/dtx line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) the eusart module generates an rcxif interrupt coincident with the wake-up event. the interrupt is generated synchronously to the q clocks in normal cpu operating modes ( figure 22-7 ), and asynchronously if the device is in sleep mode ( figure 22-8 ). the interrupt condition is cleared by reading the rcxreg register. the wue bit is automatically cleared by the low-to-high transition on the rxx line at the end of the break. this signals to the user that the break event is over. at this point, the eusart module is in idle mode waiting to receive the next character. 22.4.3.1 special considerations break character to avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. when the wake-up is enabled the function works independent of the low time on the data stream. if the wue bit is set and a valid non-zero character is received, the low time from the start bit to the first rising edge will be interpreted as the wake-up event. the remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. therefore, the initial character in the transmission must be all 0 s. this must be 10 or more bit times, 13-bit times recommended for lin bus, or any number of bit times for standard rs-232 devices. oscillator startup time oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs mode). the sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. wue bit the wake-up event causes a receive interrupt by setting the rcxif bit. the wue bit is cleared by hardware by a rising edge on rxx/dtx. the interrupt condition is then cleared by software by reading the rcxreg register and discarding its contents. to ensure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process before setting the wue bit. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 268 ? 2011-2015 microchip technology inc. figure 22-7: auto-wake-up bit (wue) timing during normal operation figure 22-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rxx/dtx line rcxif bit set by user auto cleared cleared due to user read of rcxreg note 1: the eusart remains in idle while the wue bit is set. q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rxx/dtx line rcxif bit set by user auto cleared cleared due to user read of rcxreg sleep command executed note 1 note 1: if the wake-up event requires long oscillator warm-up time, the automa tic clearing of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clo cks. 2: the eusart remains in idle while the wue bit is set. sleep ends downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 269 pic16(l)f1526/7 22.4.4 break character sequence the eusart module has the capability of sending the special break character sequences that are required by the lin bus standard. a break character consists of a start bit, followed by 12 0 bits and a stop bit. to send a break character, set the sendb and txen bits of the txxsta register. the break character trans- mission is then initiated by a write to the txxreg. the value of data written to txxreg will be ignored and all 0 s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit of the txxsta register indicates when the transmit operation is active or idle, just as it does during normal transmission. see figure 22-9 for the timing of the break character sequence. 22.4.4.1 break and sync transmit sequence the following sequence will start a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to enable the break sequence. 3. load the txxreg with a dummy character to initiate transmission (the value is ignored). 4. write 55h to txxreg to load the sync charac- ter into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware and the sync character is then transmitted. when the txxreg becomes empty, as indicated by the txxif, the next data byte can be written to txxreg. 22.4.5 receiving a break character the enhanced eusart module can receive a break character in two ways. the first method to detect a break character uses the ferr bit of the rcxsta register and the received data as indicated by rcxreg. the baud rate generator is assumed to have been initialized to the expected baud rate. a break character has been received when; rcxif bit is set ferr bit is set rcxreg = 00h the second method uses the auto-wake-up feature described in section 22.4.3 ?auto-wake-up on break? . by enabling this feature, the eusart will sample the next two transitions on rxx/dtx, cause an rcxif interrupt, and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud detect feature. for both methods, the user can set the abden bit of the baudxcon register before placing the eusart in sleep mode. figure 22-9: send break character sequence write to txxreg dummy write brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txxif bit (transmit interrupt flag) txx/ckx (pin) trmt bit (transmit shift reg. empty flag) sendb (send break control bit) sendb sampled here auto cleared downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 270 ? 2011-2015 microchip technology inc. 22.5 eusart synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. there are two signal lines in synchronous mode: a bidirectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the eusart can operate as either a master or slave device. start and stop bits are not used in synchronous transmissions. 22.5.1 synchronous master mode the following bits are used to configure the eusart for synchronous master operation: sync = 1 csrc = 1 sren = 0 (for transmit); sren = 1 (for receive) cren = 0 (for transmit); cren = 1 (for receive) spen = 1 setting the sync bit of the txxsta register configures the device for synchronous operation. setting the csrc bit of the txxsta register configures the device as a master. clearing the sren and cren bits of the rcxsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcxsta register enables the eusart. if the rxx/dtx or txx/ckx pins are shared with an analog peripheral the analog i/o functions must be disabled by clearing the corresponding ansel bits. the tris bits corresponding to the rxx/dtx and txx/ckx pins should be set. 22.5.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a master transmits the clock on the txx/ckx line. the txx/ckx pin output driver is automatically enabled when the eusart is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one clock cycle is generated for each data bit. only as many clock cycles are generated as there are data bits. 22.5.1.2 clock polarity a clock polarity option is provided for microwire compatibility. clock polarity is selected with the sckp bit of the baudxcon register. setting the sckp bit sets the clock idle state as high. when the sckp bit is set, the data changes on the falling edge of each clock and is sampled on the rising edge of each clock. clearing the sckp bit sets the idle state as low. when the sckp bit is cleared, the data changes on the rising edge of each clock and is sampled on the falling edge of each clock. 22.5.1.3 synchronous master transmission data is transferred out of the device on the rxx/dtx pin. the rxx/dtx and txx/ckx pin output drivers are automatically enabled when the eusart is configured for synchronous master transmit operation. a transmission is initiated by writing a character to the txxreg register. if the tsr still contains all or part of a previous character the new character data is held in the txxreg until the last bit of the previous character has been transmitted. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txxreg is immediately trans- ferred to the tsr. the transmission of the character commences immediately following the transfer of the data to the tsr from the txxreg. each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. note: the tsr register is not mapped in data memory, so it is not available to the user. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 271 pic16(l)f1526/7 22.5.1.4 synchronous master transmission set-up: 1. initialize the spxbrgh, spxbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. set the rxx/dtx and txx/ckx tris controls to 1 . 3. enable the synchronous master serial port by setting bits sync, spen and csrc. set the tris bits corresponding to the rxx/dtx and txx/ckx i/o pins. 4. disable receive mode by clearing bits sren and cren. 5. enable transmit mode by setting the txen bit. 6. if 9-bit transmission is desired, set the tx9 bit. 7. if interrupts are desired, set the txxie, gie and peie interrupt enable bits. 8. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 9. start transmission by loading data to the txx- reg register. figure 22-10: synchronous transmission figure 22-11: synchronous transmis sion (through txen) bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rxx/dtx write to txxreg reg txxif bit (interrupt flag) txen bit 1 1 word 2 trmt bit write word 1 write word 2 note: sync master mode, spxbrgl = 0 , continuous transmission of two 8-bit words. pin txx/ckx pin txx/ckx pin (sckp = 0 ) (sckp = 1 ) rxx/dtx pin txx/ckx pin write to txxreg reg txxif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 272 ? 2011-2015 microchip technology inc. table 22-7: summary of registers as sociated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl sckp brg16 wue abden 260 baud2con abdovf rcidl sckp brg16 wue abden 260 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 76 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 rc1sta spen rx9 sren cren adden ferr oerr rx9d 259 rc2sta spen rx9 sren cren adden ferr oerr rx9d 259 sp1brgl eusart1 baud rate generator, low byte 261* sp1brgh eusart1 baud rate generator, high byte 261* sp2brgl eusart2 baud rate generator, low byte 261* sp2brgh eusart2 baud rate generator, high byte 261* trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 trisg (1) trisg4 trisg3 trisg2 trisg1 trisg0 132 tx1reg eusart1 transmit register 250* tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 258 tx2reg eusart2 transmit register 250* tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 258 legend: = unimplemented locations, read as 0 . shaded bits are not used for synchronous master transmission. * page provides register information note 1: unimplemented, read as 1 .. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 273 pic16(l)f1526/7 22.5.1.5 synchronous master reception data is received at the rxx/dtx pin. the rxx/dtx pin output driver must be disabled by setting the corresponding tris bits when the eusart is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rcxsta register) or the continuous receive enable bit (cren of the rcxsta register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rxx/dtx pin on the trailing edge of the txx/ckx clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcxif bit is set and the character is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rcxreg. the rcxif bit remains set as long as there are un-read characters in the receive fifo. 22.5.1.6 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the txx/ckx line. the txx/ckx pin output driver must be disabled by setting the associated tris bit when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 22.5.1.7 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rcxreg is read to access the fifo. when this happens the oerr bit of the rcxsta register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rcxreg. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rcxsta register or by clearing the spen bit which resets the eusart. 22.5.1.8 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcxsta register is set the eusart will shift 9-bits into the rsr for each character received. the rx9d bit of the rcxsta register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcxreg. 22.5.1.9 synchronous master reception set-up: 1. initialize the spxbrgh, spxbrgl register pair for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. set the rxx/dtx and txx/ckx tris controls to 1 . 3. enable the synchronous master serial port by setting bits sync, spen and csrc. disable rxx/dtx and txx/ckx output drivers by setting the corresponding tris bits. 4. ensure bits cren and sren are clear. 5. if using interrupts, set the gie and peie bits of the intcon register and set rcxie. 6. if 9-bit reception is desired, set bit rx9. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcxif will be set when recep- tion of a character is complete. an interrupt will be generated if the enable bit rcxie was set. 9. read the rcxsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcxreg register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rcxsta register or by clearing the spen bit which resets the eusart. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 274 ? 2011-2015 microchip technology inc. figure 22-12: synchronous reception (master mode, sren) cren bit rxx/dtx write to bit sren sren bit rcxif bit (interrupt) read rcxreg 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . txx/ckx pin txx/ckx pin pin (sckp = 0 ) (sckp = 1 ) table 22-8: summary of registers as sociated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl sckp brg16 wue abden 260 baud2con abdovf rcidl sckp brg16 wue abden 260 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 rc1reg eusart1 receive register 253* rc1sta spen rx9 sren cren adden ferr oerr rx9d 259 rc2reg eusart2 receive register 253* rc2sta spen rx9 sren cren adden ferr oerr rx9d 259 sp1brgl eusart1 baud rate generator, low byte 261* sp1brgh eusart1 baud rate generator, high byte 261* sp2brgl eusart2 baud rate generator, low byte 261* sp2brgh eusart2 baud rate generator, high byte 261* tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 258 tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 258 legend: = unimplemented locations, read as 0 . shaded bits are not used for synchronous master reception. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 275 pic16(l)f1526/7 22.5.2 synchronous slave mode the following bits are used to configure the eusart for synchronous slave operation: sync = 1 csrc = 0 sren = 0 (for transmit); sren = 1 (for receive) cren = 0 (for transmit); cren = 1 (for receive) spen = 1 setting the sync bit of the txxsta register configures the device for synchronous operation. clearing the csrc bit of the txxsta register configures the device as a slave. clearing the sren and cren bits of the rcxsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcxsta register enables the eusart. if the rxx/dtx or txx/ckx pins are shared with an analog peripheral the analog i/o functions must be disabled by clearing the corresponding ansel bits. rxx/dtx and txx/ckx pin output drivers must be disabled by setting the corresponding tris bits. 22.5.2.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical (see section 22.5.1.3 ?synchronous master transmission? ) , except in the case of the sleep mode. if two words are written to the txxreg and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in txxreg register. 3. the txxif bit will not be set. 4. after the first character has been shifted out of tsr, the txxreg register will transfer the second character to the tsr and the txxif bit will now be set. 5. if the peie and txxie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will call the interrupt service routine. 22.5.2.2 synchronous slave transmission set-up: 1. set the sync and spen bits and clear the csrc bit. 2. set the rxx/dtx and txx/ckx tris controls to 1 . 3. clear the cren and sren bits. 4. if using interrupts, ensure that the gie and peie bits of the intcon register are set and set the txxie bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. enable transmission by setting the txen bit. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant 8 bits to the txxreg register. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 276 ? 2011-2015 microchip technology inc. table 22-9: summary of registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl sckp brg16 wue abden 260 baud2con abdovf rcidl sckp brg16 wue abden 260 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 rc1sta spen rx9 sren cren adden ferr oerr rx9d 259 rc2sta spen rx9 sren cren adden ferr oerr rx9d 259 sp1brgl eusart1 baud rate generator, low byte 261* sp1brgh eusart1 baud rate generator, high byte 261* sp2brgl eusart2 baud rate generator, low byte 261* sp2brgh eusart2 baud rate generator, high byte 261* trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 tx1reg eusart1 transmit register 250* tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 258 tx2reg eusart2 transmit register 250* tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 258 legend: = unimplemented locations, read as 0 . shaded bits are not used for synchronous slave transmission. * page provides register information. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 277 pic16(l)f1526/7 22.5.2.3 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 22.5.1.5 ?synchronous master reception? ), with the following exceptions: sleep cren bit is always set, therefore the receiver is never idle sren bit, which is a dont care in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rcxreg register. if the rcxie enable bit is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will branch to the interrupt vector. 22.5.2.4 synchronous slave reception set-up: 1. set the sync and spen bits and clear the csrc bit. 2. set the rxx/dtx and txx/ckx tris controls to 1 . 3. if using interrupts, ensure that the gie and peie bits of the intcon register are set and set the rcxie bit. 4. if 9-bit reception is desired, set the rx9 bit. 5. set the cren bit to enable reception. 6. the rcxif bit will be set when reception is complete. an interrupt will be generated if the rcxie bit was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rcxsta register. 8. retrieve the 8 least significant bits from the receive fifo by reading the rcxreg register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rcxsta register or by clearing the spen bit which resets the eusart. table 22-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl sckp brg16 wue abden 260 baud2con abdovf rcidl sckp brg16 wue abden 260 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 77 pie4 ccp10ie ccp9ie rc2ie tx2ie ccp8ie ccp7ie bcl2ie ssp2ie 80 pir1 tmr1gif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 81 pir4 ccp10if ccp9if rc2if tx2if ccp8if ccp7if bcl2if ssp2if 84 rc1reg eusart1 receive register 253* rc1sta spen rx9 sren cren adden ferr oerr rx9d 259 rc2reg eusart2 receive register 253* rc2sta spen rx9 sren cren adden ferr oerr rx9d 259 sp1brgl eusart1 baud rate generator, low byte 261* sp1brgh eusart1 baud rate generator, high byte 261* sp2brgl eusart2 baud rate generator, low byte 261* sp2brgh eusart2 baud rate generator, high byte 261* tx1sta csrc tx9 txen sync sendb brgh trmt tx9d 258 tx2sta csrc tx9 txen sync sendb brgh trmt tx9d 258 legend: = unimplemented locations, read as 0 . shaded bits are not used for synchronous slave reception. * page provides register information. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 278 ? 2011-2015 microchip technology inc. 23.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp? programming: icspclk icspdat mclr /v pp v dd v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirec- tional i/o used for transferring the serial data and the icspclk pin is the clock input. for more information on icsp? refer to the pic16f/lf151x/152x memory pro- gramming specification (ds41422). 23.1 high-voltage programming entry mode the device is placed into high-voltage programming entry mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp to v ihh . 23.2 low-voltage programming entry mode the low-voltage programming entry mode allows the pic ? flash mcus devices to be programmed using v dd only, without high voltage. when the lvp bit of configuration words is set to 1 , the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to 0 . entry into the low-voltage programming entry mode requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. if low-voltage programming is enabled (lvp = 1 ), the mclr reset function is automatically enabled and cannot be disabled. see section 6.4 ?low-power brown-out reset (lpbor)? for more information. the lvp bit can only be reprogrammed to 0 by using the high-voltage programming mode. 23.3 common programming interfaces connection to a target device is typically done through an icsp? header. a commonly found connector on development tools is the rj-11 in the 6p6c (6 pin, 6 connector) configuration. see figure 23-1 . figure 23-1: icd rj-11 style connector interface another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 23-2 . 1 2 3 4 5 6 target bottom side pc board v pp /mclr v ss icspclk v dd icspdat nc pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 279 pic16(l)f1526/7 figure 23-2: pickit? programme r style connector interface for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. see figure 23-3 for more information. figure 23-3: typical connect ion for icsp? programming 12 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect pin 1 indicator v dd v pp v ss external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). programming signals programmed v dd downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 280 ? 2011-2015 microchip technology inc. 24.0 instruction set summary each instruction is a 14-bit word containing the opera- tion code (opcode) and all required operands. the opcodes are broken into three broad categories. byte oriented bit oriented literal and control the literal and control category contains the most var- ied instruction word format. table 24-3 lists the instructions recognized by the mpasm tm assembler. all instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: subroutine takes two cycles ( call , callw ) returns from interrupts or subroutines take two cycles ( return , retlw , retfie ) program branching takes two cycles ( goto , bra , brw , btfss , btfsc , decfsz , incsfz ) one additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. one instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution rate of 1 mhz. all instruction examples use the format 0xhh to represent a hexadecimal number, where h signifies a hexadecimal digit. 24.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator d. a read operation is performed on a register even if the instruction writes to that register. table 24-1: opcode field descriptions table 24-2: abbreviation descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x dont care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1. n fsr or indf number. (0-1) mm pre-post increment-decrement mode selection field description pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 281 pic16(l)f1526/7 figure 24-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only movlp instruction only 13 5 4 0 opcode k (literal) k = 5-bit immediate value movlb instruction only 13 9 8 0 opcode k (literal) k = 9-bit immediate value bra instruction only fsr offset instructions 13 7 6 5 0 opcode n k (literal) n = appropriate fsr fsr increment instructions 13 7 6 0 opcode k (literal) k = 7-bit immediate value 13 3 2 1 0 opcode n m (mode) n = appropriate fsr m = 2-bit mode value k = 6-bit immediate value 13 0 opcode opcode only downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 282 ? 2011-2015 microchip technology inc. table 24-3: instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf asrf lslf lsrf clrf clrw comf decf incf iorwf movf movwf rlf rrf subwf subwfb swapf xorwf f, d f, d f, d f, d f, d f, d f C f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d add w and f add with carry w and f and w with f arithmetic right shift logical left shift logical right shift clear f clear w complement f decrement f increment f inclusive or w with f move f move w to f rotate left f through carry rotate right f through carry subtract w from f subtract with borrow w from f swap nibbles in f exclusive or w with f 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0011 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 01111101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffffffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z c, dc, z z c, z c, z c, z z z z z z z z c c c, dc, z c, dc, z z 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 byte oriented skip operations decfsz incfsz f, d f, d decrement f, skip if 0 increment f, skip if 0 1(2)1(2) 0000 10111111 dfffdfff ffffffff 1, 2 1, 2 bit-oriented file register operations bcf bsf f, b f, b bit clear f bit set f 11 0101 00bb01bb bfffbfff ffffffff 22 bit-oriented skip operations btfsc btfss f, b f, b bit test f, skip if clear bit test f, skip if set 1 (2) 1 (2) 0101 10bb11bb bfff bfff ffffffff 1, 2 1, 2 literal operations addlw andlw iorlw movlb movlp movlw sublw xorlw kk k k k k k k add literal and w and literal with w inclusive or literal with w move literal to bsr move literal to pclath move literal to w subtract w from literal exclusive or literal with w 11 1 1 1 1 1 1 1111 11 00 11 11 11 11 11101001 1000 0000 0001 0000 1100 1010 kkkkkkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkkkkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z z z c, dc, z z note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 283 pic16(l)f1526/7 table 24-3: instruction set (continued) mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb control operations bra brw call callw goto retfie retlw return kC k C k k k C relative branch relative branch with w call subroutine call subroutine with w go to address return from interrupt return with literal in w return from subroutine 22 2 2 2 2 2 2 1100 10 00 10 00 11 00 001k0000 0kkk 0000 1kkk 0000 0100 0000 kkkk0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk1011 kkkk 1010 kkkk 1001 kkkk 1000 inherent operations clrwdt nop option reset sleep tris CC C C C f clear watchdog timer no operation load option_reg register with w software device reset go into standby mode load tris register with w 11 1 1 1 1 0000 00 00 00 00 00000000 0000 0000 0000 0000 01100000 0110 0000 0110 0110 01000000 0010 0001 0011 0fff to , pd to , pd c-compiler optimized addfsr moviw movwi n, k n mm k[n] n mm k[n] add literal k to fsrn move indirect fsrn to w with pre/post inc/dec modifier, mm move indfn to w, indexed indirect. move w to indirect fsrn with pre/post inc/dec modifier, mm move w to indfn, indexed indirect. 11 1 1 1 1100 11 00 11 00010000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmmkkkk 1nmm kkkk zz 2, 3 2 2, 3 2 note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle i s executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 284 ? 2011-2015 microchip technology inc. 24.2 instruction descriptions addfsr add literal to fsrn syntax: [ label ] addfsr fsrn, k operands: -32 ? k ? 31 n ? [ 0, 1] operation: fsr(n) + k ? fsr(n) status affected: none description: the signed 6-bit literal k is added to the contents of the fsrnh:fsrnl register pair. fsrn is limited to the range 0000h - ffffh. moving beyond these bounds will cause the fsr to wrap-around. addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the 8-bit literal k and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. addwfc add w and carry bit to f syntax: [ label ] addwfc f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: c, dc, z description: add w, the carry flag and data mem- ory location f. if d is 0 , the result is placed in w. if d is 1 , the result is placed in data memory location f. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are anded with the 8-bit literal k. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. asrf arithmetic right shift syntax: [ label ] asrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register f are shifted one bit to the right through the carry flag. the msb remains unchanged. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in reg- ister f. register f c downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 285 pic16(l)f1526/7 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit b in register f is cleared. bra relative branch syntax: [ label ] bra label [ label ] bra $+k operands: -256 ? label - pc + 1 ? 255 -256 ? k ? 255 operation: (pc) + 1 + k ? pc status affected: none description: add the signed 9-bit literal k to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + k. this instruction is a 2-cycle instruc- tion. this branch has a limited range. brw relative branch with w syntax: [ label ] brw operands: none operation: (pc) + (w) ? pc status affected: none description: add the contents of w (unsigned) to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + (w). this instruction is a 2-cycle instruc- tion. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit b in register f is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit b in register f is 1 , the next instruction is executed. if bit b, in register f, is 0 , the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit b in register f is 0 , the next instruction is executed. if bit b is 1 , then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 286 ? 2011-2015 microchip technology inc. call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<6:3>) ? pc<14:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a 2-cycle instruc- tion. callw subroutine call with w syntax: [ label ] callw operands: none operation: (pc) +1 ? tos, (w) ? pc<7:0>, (pclath<6:0>) ?? pc<14:8> status affected: none description: subroutine call with w. first, the return address (pc + 1) is pushed onto the return stack. then, the con- tents of w is loaded into pc<7:0>, and the contents of pclath into pc<14:8>. callw is a 2-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register f are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register f are com- plemented. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 287 pic16(l)f1526/7 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register f are decre- mented. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. if the result is 1 , the next instruction is executed. if the result is 0 , then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<6:3> ? pc<14:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a 2-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register f are incre- mented. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register f are incre- mented. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. if the result is 1 , the next instruction is executed. if the result is 0 , a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are ored with the 8-bit literal k. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with regis- ter f. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 288 ? 2011-2015 microchip technology inc. lslf logical left shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? c (f<6:0>) ? dest<7:1> 0 ? dest<0> status affected: c, z description: the contents of register f are shifted one bit to the left through the carry flag. a 0 is shifted into the lsb. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f. lsrf logical right shift syntax: [ label ] lsrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: 0 ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register f are shifted one bit to the right through the carry flag. a 0 is shifted into the msb. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f. register f 0 c register f c 0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 ,destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 289 pic16(l)f1526/7 moviw move indfn to w syntax: [ label ] moviw ++fsrn [ label ] moviw --fsrn [ label ] moviw fsrn++ [ label ] moviw fsrn-- [ label ] moviw k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: indfn ? w effective address is determined by fsr + 1 (preincrement) fsr - 1 (predecrement) fsr + k (relative offset) after the move, the fsr value will be either: fsr + 1 (all increments) fsr - 1 (all decrements) unchanged status affected: z mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 31 operation: k ? bsr status affected: none description: the 5-bit literal k is loaded into the bank select register (bsr). movlp move literal to pclath syntax: [ label ] movlp k operands: 0 ? k ? 127 operation: k ? pclath status affected: none description: the 7-bit literal k is loaded into the pclath register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the 8-bit literal k is loaded into w reg- ister. the dont cares will assemble as 0 s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register f. words: 1 cycles: 1 example: movwf option_reg before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 290 ? 2011-2015 microchip technology inc. movwi move w to indfn syntax: [ label ] movwi ++fsrn [ label ] movwi --fsrn [ label ] movwi fsrn++ [ label ] movwi fsrn-- [ label ] movwi k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: w ? indfn effective address is determined by fsr + 1 (preincrement) fsr - 1 (predecrement) fsr + k (relative offset) after the move, the fsr value will be either: fsr + 1 (all increments) fsr - 1 (all decrements) unchanged status affected: none mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. the increment/decrement operation on fsrn will not affect any status bits. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop option load option_reg register with w syntax: [ label ] option operands: none operation: (w) ? option_reg status affected: none description: move data from w register to option_reg register. words: 1 cycles: 1 example: option before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f reset software reset syntax: [ label ] reset operands: none operation: execute a device reset. resets the r i flag of the pcon register. status affected: none description: this instruction provides a way to execute a hardware reset by soft- ware. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 291 pic16(l)f1526/7 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a 2-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the 8-bit literal k. the program counter is loaded from the top of the stack (the return address). this is a 2-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a 2-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register f are rotated one bit to the left through the carry flag. if d is 0 , the result is placed in the w register. if d is 1 , the result is stored back in register f. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w = 1100 1100 c= 1 register f c downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 292 ? 2011-2015 microchip technology inc. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register f are rotated one bit to the right through the carry flag. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2s com- plement method) from the 8-bit literal k. the result is placed in the w regis- ter. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2s complement method) w register from register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. subwfb subtract w from f with borrow syntax: subwfb f {,d} operands: 0 ? f ? 127 d ? [0,1] operation: (f) C (w) C (b ) ?? dest status affected: c, dc, z description: subtract w and the borrow flag (carry) from register f (2s comple- ment method). if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0> downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 293 pic16(l)f1526/7 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter f are exchanged. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed in register f. tris load tris register with w syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register f status affected: none description: move data from w register to tris register. when f = 5, trisa is loaded. when f = 6, trisb is loaded. when f = 7, trisc is loaded. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xored with the 8-bit literal k. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in regis- ter f. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 294 ? 2011-2015 microchip technology inc. 25.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias ................................................................................................. ...... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss , pic16f1526/7 .......................................................................... -0.3v to +6.5v voltage on v cap with respect to v ss , pic16f1526/7 ........................................................................ -0.3v to +4.0v voltage on v dd with respect to v ss , pic16lf1526/7 ........................................................................ -0.3v to +4.0v voltage on mclr with respect to vss ................................................................................................. -0.3v to +9.0v voltage on all other pins with respect to v ss ............................................................................ -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin, -40c ? t a ? +85c for industrial............................................................... 350 ma maximum current out of v ss pin, -40c ? t a ? +125c for extended ............................................................ 140 ma maximum current into v dd pin, -40c ? t a ? +85c for industrial.................................................................. 350 ma maximum current into v dd pin, -40c ? t a ? +125c for extended ............................................................... 140 ma clamp current, i k (v pin < 0 or v pin > v dd ) ???????????????????????????????????????????????????????????????????????????????????????????????????? ?????????????? 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 50 ma maximum output current sourced by any i/o pin.................................................................................. ............. 50 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd C ? i oh } + ? {(v dd C v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 295 pic16(l)f1526/7 figure 25-1: pic16f1526/7 voltage frequency graph, -40c ? t a ?? +125c figure 25-2: pic16lf1526/7 voltage frequency graph, -40c ? t a ?? +125c note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 25-1 for each oscillator modes supported frequencies. 0 2.3 frequency (mhz) v dd (v) 42 0 10 16 5.5 2.5 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 25-1 for each oscillator modes supported frequencies. 1.8 0 2.5 frequency (mhz) v dd (v) 42 0 10 16 3.6 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 296 ? 2011-2015 microchip technology inc. figure 25-3: hfintosc frequency accuracy over device v dd and temperature 125 25 2.0 0 60 85 v dd (v) 4.0 5.0 4.5 temperature ( c ) 2.5 3.0 3.5 5.5 1.8 -40 -15% to +12.5% -15% to +12.5% 8% 6.5% downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 297 pic16(l)f1526/7 figure 25-4: por and por rearm with slow rising v dd 25.1 dc characteristics: supply voltage pic16lf1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. sym. characteristic min. typ? max. units conditions d001 v dd supply voltage (v ddmin , v ddmax ) 1.8 2.5 3.6 3.6 vv f osc ? 16 mhz f osc ? 20 mhz d001 2.3 2.5 5.5 5.5 vv f osc ? 16 mhz f osc ? 20 mhz d002* v dr ram data retention voltage (1) 1.5 v device in sleep mode d002* 1.7 v device in sleep mode d002a* v por * power-on reset release voltage 1 . 6 v d002b* v porr * power-on reset rearm voltage 0 . 8 v d002b* 1.5 v d003 v adfvr fixed voltage reference voltage for adc -8 6 % 1.024v, v dd ? 2.5v 2.048v, v dd ? 2.5v 4.096v, v dd ? 4.75v d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section 6.1 ?power-on reset (por)? for details. * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. v dd v por v porr v ss v ss npor (1) t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 298 ? 2011-2015 microchip technology inc. 25.2 dc characteristics: supply current (i dd ) pic16lf1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2, 3) d009 ldo regulator 350 ? a device operating at 8 mhz 13 ? a sleep v regpm = 0 0.3 ? a sleep v regpm = 1 d010 10 20 ? a1 . 8 f osc = 32 khz lp oscillator -40c ? t a ? +85c 1 5 35 ? a3 . 0 d010 20 35 ? a 2.3 f osc = 32 khz lp oscillator -40c ? t a ? +85c 30 45 ? a 3.0 40 50 ? a 5.0 d011 70 100 ? a1 . 8f osc = 1 mhz xt oscillator 130 200 ? a3 . 0 d011 120 180 ? a 2.3 f osc = 1 mhz xt oscillator 160 240 ? a 3.0 240 360 ? a 5.0 d012 170 245 ? a1 . 8f osc = 4 mhz xt oscillator 300 440 ? a3 . 0 d012 290 475 ? a 2.3 f osc = 4 mhz xt oscillator 380 525 ? a 3.0 460 675 ? a 5.0 d013 25 35 ? a1 . 8f osc = 500 khz external clock (ecl), low-power mode 4 2 60 ? a3 . 0 d013 50 65 ? a 2.3 f osc = 500 khz external clock (ecl), low-power mode 60 80 ? a 3.0 70 85 ? a 5.0 * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 0.1 f capacitor on v cap pin (pic16f1526/7). 4: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ?? downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 299 pic16(l)f1526/7 supply current (i dd ) (1, 2, 3) d014 150 225 ? a1 . 8f osc = 4 mhz external clock (ecm) medium-power mode 280 400 ? a3 . 0 d014 240 325 ? a 2.3 f osc = 4 mhz external clock (ecm) medium-power mode 325 450 ? a 3.0 410 550 ? a 5.0 d014a 1.4 1.8 ma 3.0 f osc = 20 mhz external clock (ech) high-power mode 1 . 6 2.3 ma 3.6 d014a 1.45 1.9 ma 3.0 f osc = 20 mhz external clock (ech) high-power mode 1.7 2.4 ma 5.0 d015 6 . 0 15 ? a1 . 8f osc = 31 khz lfintosc -40c ? t a ? +85c 15.0 35 ? a3 . 0 d015 18 28 ? a 2.3 f osc = 31 khz lfintosc -40c ? t a ? +85c 24 40 ? a 3.0 26 45 ? a 5.0 d016 245 400 ? a1 . 8f osc = 500 khz hfintosc 320 425 ? a3 . 0 d016 300 340 ? a 2.3 f osc = 500 khz hfintosc 340 370 ? a 3.0 380 450 ? a 5.0 d017* 0.6 0.9 ma 1.8 f osc = 8 mhz hfintosc 0 . 9 1.1 ma 3.0 d017* 0.7 1.0 ma 2.3 f osc = 8 mhz hfintosc 0.9 1.2 ma 3.0 1.1 1.3 ma 5.0 25.2 dc characteristics: supply current (i dd ) (continued) pic16lf1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 0.1 f capacitor on v cap pin (pic16f1526/7). 4: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ?? downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 300 ? 2011-2015 microchip technology inc. supply current (i dd ) (1, 2, 3) d018 0.9 1.4 ma 1.8 f osc = 16 mhz hfintosc 1 . 5 1.8 ma 3.0 d018 1.0 1.5 ma 2.3 f osc = 16 mhz hfintosc 1.5 1.8 ma 3.0 1.7 1.9 ma 5.0 d020 1.7 2.0 ma 3.0 f osc = 20 mhz hs oscillator 2 . 1 2.5 ma 3.6 d020 1.8 2.1 ma 3.0 f osc = 20 mhz hs oscillator 2.2 2.7 ma 5.0 d021 190 240 ? a1 . 8f osc = 4 mhz extrc (note 4) 340 400 ? a3 . 0 d021 250 350 ? a 2.3 f osc = 4 mhz extrc (note 4) 340 440 ? a 3.0 425 525 ? a 5.0 25.2 dc characteristics: supply current (i dd ) (continued) pic16lf1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 0.1 f capacitor on v cap pin (pic16f1526/7). 4: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ?? downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 301 pic16(l)f1526/7 25.3 dc characteristics: power-down currents (i pd ) pic16lf1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note power-down currents (i pd ) (2) d022 base i pd 0.02 1.0 8.0 ? a 1.8 wdt, bor, fvr and sosc disabled, all peripherals inactive 0.03 2.0 9.0 ? a3 . 0 d022 base i pd 0.20 3.0 10 ? a 2.3 wdt, bor, fvr and sosc disabled, all peripherals inactive, low-power regulator active 0.30 4.0 12 ? a 3.0 0.47 6.0 15 ? a 5.0 d023 0.50 6.0 14 ? a 1.8 wdt current (note 1) 0.80 7.0 17 ? a 3.0 d023 0.50 6.0 15 ? a 2.3 wdt current (note 1) vregpm = 1 0.77 7.0 20 ? a 3.0 0.85 8.0 22 ? a 5.0 d023a 8.5 24 27 ? a 3.0 fvr current (note 1) d023a 19 27 37 ? a 3.0 fvr current (note 1) vregpm = 1 20 29 45 ? a 5.0 d024 8.0 17 20 ? a 3.0 bor current (note 1) d024 8.0 17 30 ? a 3.0 bor current (note 1) vregpm = 1 9.0 20 40 ? a 5.0 d024a 0.30 4.0 8.0 ? a 3.0 lpbor current (note 1) d024a 0.30 4.0 14 ? a 3.0 lpbor current (note 1) vregpm = 1 0.45 8.0 17 ? a 5.0 d025 0.3 5.0 9.0 ? a 1.8 sosc current (note 1) 0 . 58 . 5 1 2 ? a3 . 0 d025 1.1 6.0 10 ? a 2.3 sosc current (note 1) vregpm = 1 1.3 8.5 20 ? a 3.0 1.4 10 25 ? a 5.0 d026* 0.10 1.0 9.0 ? a 1.8 adc current (note 1, 3) , no conversion in progress 0.10 2.0 10 ? a3 . 0 d026* 0.16 3.0 10 ? a 2.3 adc current (note 1, 3) , no conversion in progress vregpm = 1 0.40 4.0 11 ? a 3.0 0.50 6.0 16 ? a 5.0 * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral ? current can be determined by subtracting the base i pd current from this limit. max. values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: adc clock source is f rc . downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 302 ? 2011-2015 microchip technology inc. power-down base current (i pd ) (2) d026a* 250 ? a 1.8 adc current (note 1, 3) , conversion in progress 250 ? a3 . 0 d026a* 280 ? a 2.3 adc current (note 1, 3) , conversion in progress vregpm = 1 280 ? a 3.0 280 ? a 5.0 25.3 dc characteristics: power-down currents (i pd ) (continued) pic16lf1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1526/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral ? current can be determined by subtracting the base i pd current from this limit. max. values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: adc clock source is f rc . downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 303 pic16(l)f1526/7 25.4 dc characteristics: i/o ports dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d030 with ttl buffer 0.8 v 4.5v ? v dd ? 5.5v d030a 0.15 v dd v1.8v ? v dd ? 4.5v d031 with schmitt trigger buffer 0.2 v dd v2.0v ? v dd ? 5.5v with i 2 c levels 0.3 v dd v with smbus levels 0.8 v 2.7v ? v dd ? 5.5v d032 mclr , osc1 (rc mode) 0.2 v dd v (note 1) d033 osc1 (hs mode) 0.3 v dd v v ih input high voltage i/o port: d040 with ttl buffer 2.0 v 4.5v ? v dd ?? 5.5v d040a 0.25 v dd + 0.8 v 1 . 8 v ? v dd ? 4.5v d041 with schmitt trigger buffer 0.8 v dd v 2 . 0 v ? v dd ? 5.5v with i 2 c levels 0.7 v dd v with smbus levels 2.1 v 2.7v ? v dd ? 5.5v d042 mclr 0.8 v dd v d043a osc1 (hs mode) 0.7 v dd v d043b osc1 (rc mode) 0.9 v dd v v dd ? 2.0v (note 1) i il input leakage current (2) d060 i/o ports 5 125 na v ss ? v pin ? v dd , pin at high impedance, 85c 5 1000 na v ss ? v pin ? v dd , pin at high impedance, 125c d061 mclr (3) 5 0 2 0 0n a v ss ? v pin ? v dd pin at high impedance, 85c i pur weak pull-up current d070* 25 25 100140 200300 ? a ? a v dd = 3.3v, v pin = v ss v dd = 5.0v, v pin = v ss v ol output low voltage (4) d080 i/o ports 0 . 6v i ol = 8 ma, v dd = 5v i ol = 6 ma, v dd = 3.3v i ol = 1.8 ma, v dd = 1.8v v oh output high voltage (4) d090 i/o ports v dd - 0.7 v i oh = 3.5 ma, v dd = 5v i oh = 3 ma, v dd = 3.3v i oh = 1 ma, v dd = 1.8v * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an exte rnal clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 304 ? 2011-2015 microchip technology inc. capacitive loading specs on i/o pins d101* cosc2 osc2 pin 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101a* c io all i/o pins 50 pf d102 v cap capacitor charging charging current 200 ? a d102a source/sink capability when charging is complete 0.0 ma 25.4 dc characteristics: i/o ports (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an exte rnal clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 305 pic16(l)f1526/7 25.5 memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions program memory programming specifications d110 v ihh voltage on mclr /v pp pin 8.0 9.0 v (note 2) d111 i ddp supply current during programming 1 0m a d112 v be v dd for bulk erase 2.7 v ddmax v d113 v pew v dd for write or row erase v ddmin v ddmax v d114 i pppgm current on mclr /v pp during erase/write 1 . 0m a d115 i ddpgm current on v dd during erase/write 5.0 m a program flash memory d121 e p cell endurance 10k e/w -40 ? c to +85 ? c (note 1) d122 v prw v dd for read/write v ddmin v ddmax v d123 t iw self-timed write cycle time 2 2.5 ms d124 t retd characteristic retention 40 year provided no other specifications are violated d125 e hefc high-endurance flash cell 100k e/w 0 ? c to +60 ? c lower byte last 128 addresses ? data in typ column is at 3.0v, 25c unless otherwise stated. these para meters are for design guidance only and are not tested. note 1: self-write and block erase. 2: required only if single-supply programming is disabled. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 306 ? 2011-2015 microchip technology inc. 25.6 thermal considerations standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 48.3 ? c/w 64-pin tqfp (10x10 mm) package 28.0 ? c/w 64-pin qfn (9x9 mm) package th02 ? jc thermal resistance junction to case 26.1 ? c/w 64-pin tqfp (10x10 mm) package 1.2 ? c/w 64-pin qfn (9x9 mm) package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation w pd = p internal + p i / o th05 p internal internal power dissipation w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power w p der = pd max (t j - t a )/ ? ja (2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature; t j = junction temperature. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 307 pic16(l)f1526/7 25.7 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 25-5: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdix sc sckx do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ff a l l pp e r i o d hh i g h rr i s e i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins, 15 pf for osc2 output load condition pin downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 308 ? 2011-2015 microchip technology inc. 25.8 ac characteristics: pic16(l)f1526/7-i/e figure 25-6: clock timing table 25-1: clock oscillator timing requirements osc1/clkin osc2/clkout q4 q1 q2 q3 q4 q1 os02 os03 os04 os04 osc2/clkout (lp,xt,hs modes) (clkout mode) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions os01 f osc external clkin frequency (1) dc 0.5 mhz external clock (ecl) dc 4 mhz external clock (ecm) dc 20 mhz external clock (ech) oscillator frequency (1) 32.768 khz lp oscillator 0.1 4 mhz xt oscillator 1 4 mhz hs oscillator 1 20 mhz hs oscillator, v dd > 2.7v dc 4 mhz rc oscillator, v dd > ? 2.0v os02 t osc external clkin period (1) 27 ?? s lp oscillator 250 ? ns xt oscillator 50 ? ns hs oscillator 50 ? ns external clock (ec) oscillator period (1) 30.5 ? s lp oscillator 250 10,000 ns xt oscillator 50 1,000 ns hs oscillator 250 ns rc oscillator os03 t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc os04* tosh, tosl external clkin high, external clkin low 2 ? s lp oscillator 100 ns xt oscillator 20 ns hs oscillator os05* tosr, tosf external clkin rise, external clkin fall 0 ns lp oscillator 0 ns xt oscillator 0 ns hs oscillator * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at min values wi th an external clock applied to osc1 pin. when an external clock input is used, the max cycle time limit is dc (no clock) for all devices. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 309 pic16(l)f1526/7 table 25-2: oscillator parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic freq. tolerance min. typ? max. units conditions os08 hf osc internal calibrated hfintosc frequency (note 1) ? 6.5% 16.0 mhz v dd = 3.0v at 25c (note 2) os09 lf osc internal lfintosc frequency 31 khz (note 3) os10* t iosc st hfintosc wake-up from sleep start-up time 5 15 ? svregpm = 0 * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. 2: see figure 25-3 , hfintosc frequency accuracy over v dd and temperature. 3: see figure 26-60 and figure 26-61 , lfintosc frequency characteristics over v dd and temperature. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 310 ? 2011-2015 microchip technology inc. figure 25-7: clkout and i/o timing table 25-3: clkout and i/o timing parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os11 tosh2ckl f osc ? to clkout ? (1) 7 0n s v dd = 3.3-5.0v os12 tosh2ckh f osc ? to clkout ? (1) 7 2n s v dd = 3.3-5.0v os13 tckl2iov clkout ? to port out valid (1) 2 0n s os14 tiov2ckh port input valid before clkout ? (1) t osc + 200 ns ns os15 tosh2iov fosc ? (q1 cycle) to port out valid 50 70* ns v dd = 3.3-5.0v os16 tosh2ioi fosc ? (q2 cycle) to port input invalid (i/o in setup time) 50 ns v dd = 3.3-5.0v os17 tiov2osh port input valid to fosc ?? (q2 cycle) (i/o in setup time) 20 ns os18* tior port output rise time 4015 7232 ns v dd = 1.8v v dd = 3.3-5.0v os19* tiof port output fall time 2815 5530 ns v dd = 1.8v v dd = 3.3-5.0v os20* tinp int pin input high or low time 25 ns os21* tioc interrupt-on-change new input level time 25 ns * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 311 pic16(l)f1526/7 figure 25-8: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 25-9: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out osc start-up time internal reset (1) watchdog timer 33 32 30 31 34 i/o pins 34 note 1: asserted low. reset (1) v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) note 1: 64 ms delay only if pwrte bit in the configuration words is programmed to 0 . 2 ms delay if pwrte = 0 . reset (due to bor) v bor and v hyst 37 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 312 ? 2011-2015 microchip technology inc. table 25-4: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 30 t mc lm c l r pulse width (low) 2 ? s 30a t mc l r 31 t wdtlp low-power watchdog timer time-out period 10 16 27 ms v dd = 3.3v-5v, 1:512 prescaler used 32 t ost oscillator start-up timer period (1) 1024 tosc (note 3) 33* t pwrt power-up timer period, pwrte = 0 40 65 140 ms 34* t ioz i/o high impedance from mclr low or watchdog timer reset 2 . 0 ? s 35 v bor brown-out reset voltage (2) 2.55 2.35 1.80 2.70 2.45 1.90 2.85 2.58 2.00 vv v borv = 0 , pic16(l)f1526/7 borv = 1 , pic16f1526/7 borv = 1 , pic16lf1526/7 36* v hyst brown-out reset hysteresis 0 25 60 mv -40c to +85c 37* t bordc brown-out reset dc response time 133 5 ? sv dd ? v bor 38 v lpbor low-power brown-out reset voltage 1.8 2.1 2.5 v lpbor = 1 * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: by design, the oscillator start-up timer (ost) counts the first 1024 cycles, independent of frequency. 2: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 313 pic16(l)f1526/7 figure 25-10: timer0 and timer1 external clock timings table 25-5: timer0 and timer1 external clock requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ns n = prescale value 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ns synchronous, with prescaler 15 ns asynchronous 30 ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ns synchronous, with prescaler 15 ns asynchronous 30 ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ns n = prescale value asynchronous 60 ns 48 f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit soscen) 32.4 32.768 33.1 khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc 7 t osc timers in sync mode * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 314 ? 2011-2015 microchip technology inc. figure 25-11: capture/com pare/pwm timings (ccp) table 25-6: capture/compare/pwm requirements (ccp) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions cc01* tccl ccp input low time no prescaler 0.5t cy + 20 ns with prescaler 20 ns cc02* tcch ccp input high time no prescaler 0.5t cy + 20 ns with prescaler 20 ns cc03* tccp ccp input period 3t cy + 40 n ns n = prescale value * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 25-5 for load conditions. (capture mode) cc01 cc02 cc03 ccp downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 315 pic16(l)f1526/7 table 25-7: analog-to-digital converter (adc) characteristics (1,2,3) table 25-8: adc conversion requirements standard operating conditions (unless otherwise stated) operating temperature tested at 25c param no. sym. characteristic min. typ? max. units conditions ad01 n r resolution 10 bit ad02 e il integral error 1 1.7 lsb v ref = 3.0v ad03 e dl differential error 1 1 lsb no missing codes v ref = 3.0v ad04 e off offset error 1 2.5 lsb v ref = 3.0v ad05 e gn gain error 1 2.0 lsb v ref = 3.0v ad06 v ref reference voltage (4) 1.8 v dd vv ref = (v ref + minus v ref -) ad07 v ain full-scale range v ss v ref v ad08 z ain recommended impedance of analog voltage source 1 0k ? can go higher if external 0.01 ? f capacitor is present on input pin. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the adc conversion result never decreases with an increase in the input voltage and has no missing codes. 3: adc v ref is from external v ref , v dd pin or fvr, whichever is selected as reference input. 4: adc reference voltage (ref+) is the selected reference input, v ref + pin, v dd pin or the fvr buffer1. when the fvr is selected as the reference input, the fvr buffer1 output selection must be 2.048v or 4.096v (adfvr<1:0> = 1x ). standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad130* t ad adc clock period 1.0 9.0 ? sf osc -based adc internal rc oscillator period 1.0 2.0 6.0 ? s adcs<2:0> = x11 (adc frc mode) ad131 t cnv conversion time (not including acquisition time) (1) 1 1 t ad set go/done bit to conversion complete ad132* t acq acquisition time 5.0 ? s ad133 t hcd holding capacitor disconnect 0.5*t ad + 40 ns (0.5*t ad + 40 ns) to (1.5*t ad + 40 ns) adcs<2:0> ? x11 (f osc -based) adcs<2:0> = x11 (adc frc mode) * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the adres register may be read on the following t cy cycle. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 316 ? 2011-2015 microchip technology inc. figure 25-12: adc conversion timing (normal mode) figure 25-13: adc conversion timing (sleep mode) ad131 ad130 bsf adcon0, go q4 adc clk adc data adres adif go sample old_data sampling stopped done new_data 765 3210 note 1: if the adc clock source is selected as rc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. 1 t cy 4 ad134 (t osc /2 (1) ) 1 t cy ad132 ad132 ad131 ad130 bsf adcon0, go q4 adc clk adc data adres adif go sample old_data sampling stopped done new_data 7 5 3210 note 1: if the adc clock source is selected as rc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. ad134 4 6 1 t cy (t osc /2 + t cy (1) ) 1 t cy downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 317 pic16(l)f1526/7 table 25-9: low dropout (ldo) regulator characteristics figure 25-14: usart synchronous transmission (master/slave) timing table 25-10: usart synchronous tran smission requirements standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ldo01 ldo regulation voltage 3.0 v ldo02 ldo external capacitor 0.1 1 ? f ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us120 t ck h2 dt v sync xmit (master and slave) clock high to data-out valid 3.0-5.5v 80 ns 1.8-5.5v 100 ns us121 t ckrf clock out rise time and fall time (master mode) 3.0-5.5v 45 ns 1.8-5.5v 50 ns us122 t dtrf data-out rise time and fall time 3.0-5.5v 45 ns 1.8-5.5v 50 ns note: refer to figure 25-5 for load conditions. us121 us121 us120 us122 ck dt downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 318 ? 2011-2015 microchip technology inc. figure 25-15: usart synchrono us receive (master/slave) timing table 25-11: usart synchronous receive requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us125 t dt v2 ckl sync rcv (master and slave) data-hold before ck ? (dt hold time) 10 ns us126 t ck l2 dtl data-hold after ck ? (dt hold time) 15 ns note: refer to figure 25-5 for load conditions. us125 us126 ck dt downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 319 pic16(l)f1526/7 figure 25-16: spi master mode timing (cke = 0 , smp = 0 ) figure 25-17: spi master mode timing (cke = 1 , smp = 1 ) ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 25-5 for load conditions. ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp81 sp71 sp72 sp74 sp75, sp76 sp78 sp80 msb sp79 sp73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 25-5 for load conditions. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 320 ? 2011-2015 microchip technology inc. figure 25-18: spi slav e mode timing (cke = 0 ) figure 25-19: spi slav e mode timing (cke = 1 ) ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp77 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in sp83 note: refer to figure 25-5 for load conditions. ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp82 sp74 sp75, sp76 msb bit 6 - - - - - -1 lsb sp77 msb in bit 6 - - - -1 lsb in sp80 sp83 note: refer to figure 25-5 for load conditions. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 321 pic16(l)f1526/7 table 25-12: spi mode requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. symbol characteristic min. typ? max. units conditions sp70* t ss l2 sc h, t ss l2 sc l ss ? to sck ? or sck ? input 2.25 t cy n s sp71* t sc h sck input high time (slave mode) t cy + 20 ns sp72* t sc l sck input low time (slave mode) t cy + 20 ns sp73* t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ns sp74* t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ns sp75* t do r sdo data output rise time 3.0-5.5v 10 25 ns 1.8-5.5v 25 50 ns sp76* t do f sdo data output fall time 10 25 ns sp77* t ss h2 do zss ? to sdo output high-impedance 10 50 ns sp78* t sc r sck output rise time (master mode) 3.0-5.5v 10 25 ns 1.8-5.5v 25 50 ns sp79* t sc f sck output fall time (master mode) 10 25 ns sp80* t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 3.0-5.5v 50 ns 1.8-5.5v 145 ns sp81* t do v2 sc h, t do v2 sc l sdo data output setup to sck edge tcy ns sp83* t sc h2 ss h, t sc l2 ss h ss ?? after sck edge 1.5t cy + 40 n s * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 322 ? 2011-2015 microchip technology inc. figure 25-20: i 2 c bus start/stop bits timing figure 25-21: i 2 c bus data timing note : refer to figure 25-5 for load conditions. sp91 sp92 sp93 sclx sdax start condition stop condition sp90 table 25-13: i 2 c bus start/stop bits requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. typ. max. units conditions sp90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 sp91* t hd : sta start condition 100 khz mode 4000 ns after this period, the first clock pulse is generated hold time 400 khz mode 600 sp92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 sp93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 25-5 for load conditions. sp90 sp91 sp92 sp100 sp101 sp103 sp106 sp107 sp109 sp109 sp110 sp102 sclx sdax in sdax out downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 323 pic16(l)f1526/7 table 25-14: i 2 c bus data requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions sp100* t high clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy sp101* t low clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy sp102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf sp103* t f sda and scl fall time 100 khz mode 250 ns 400 khz mode 20 + 0.1c b 250 ns c b is specified to be from 10-400 pf sp106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 ? s sp107* t su : dat data input setup time 100 khz mode 250 ns (note 2) 400 khz mode 100 ns sp109* t aa output valid from clock 100 khz mode 3500 ns (note 1) 400 khz mode ns sp110* t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s sp111 c b bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined regio n (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat ?? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 324 ? 2011-2015 microchip technology inc. 26.0 dc and ac characteristics graphs and charts the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range. ? typical? represents the mean of the distribution at 25 ? c. ?maximum?, ?max.?, ?minimum? or ?min.? represents (mean + 3 ? ) or (mean - 3 ? ) respectively, where ? is a standard deviation, over each temperature range. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 325 pic16(l)f1526/7 figure 26-1: i dd , lp oscillator, f osc = 32 khz, pic16lf1526 only figure 26-2: i dd , lp oscillator, f osc = 32 khz, pic16f1526/7 only typical max. 0 5 10 15 20 25 30 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 5 10 15 20 25 30 35 40 45 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 326 ? 2011-2015 microchip technology inc. figure 26-3: i dd typical, xt and extrc oscillator, pic16lf1526 only figure 26-4: i dd maximum, xt and extrc oscillator, pic16lf1526 only 4 mhz xt 1 mhz extrc 1 mhz xt 0 50 100 150 200 250 300 350 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) typical: 25c 4 mhz xt 1 mhz extrc 1 mhz xt 0 50 100 150 200 250 300 350 400 450 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 327 pic16(l)f1526/7 figure 26-5: i dd typical, xt and extrc oscillator, pic16f1526/7 only figure 26-6: i dd maximum, xt and extrc oscillator, pic16f1526/7 only 4 mhz extrc 4 mhz xt 1 mhz extrc 1 mhz xt 0 50 100 150 200 250 300 350 400 450 500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) typical: 25c 4 mhz extrc 4 mhz xt 1 mhz extrc 1 mhz xt 0 100 200 300 400 500 600 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 328 ? 2011-2015 microchip technology inc. figure 26-7: i dd , external clock (ecl), low-power mode, f osc = 32 khz, pic16lf1526 only figure 26-8: i dd , external clock (ecl), low-power mode, f osc = 32 khz, pic16f1526/7 only typical max. 0 5 10 15 20 25 30 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 5 10 15 20 25 30 35 40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (a) v dd (v) max: 85c + 3 1 typical: 25c downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 329 pic16(l)f1526/7 figure 26-9: i dd , external clock (ecl), low-power mode, f osc = 500 khz, pic16lf1526 only figure 26-10: i dd , external clock (ecl), low-power mode, f osc = 500 khz, pic16f1526/7 only max. typical 0 10 20 30 40 50 60 70 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 10 20 30 40 50 60 70 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 330 ? 2011-2015 microchip technology inc. figure 26-11: i dd typical, external clock (ecm), medium-power mode, pic16lf1526 only figure 26-12: i dd maximum, external clock (ecm), medium-power mode, pic16lf1526 only 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) typical: 25c 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 450 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 331 pic16(l)f1526/7 figure 26-13: i dd typical, external clock (ecm), medium-power mode, pic16f1526/7 only figure 26-14: i dd maximum, external clock (ecm), medium-power mode, pic16f1526/7 only 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 450 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) typical: 25c 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 450 500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 332 ? 2011-2015 microchip technology inc. figure 26-15: i dd typical, external clock (ech), high-power mode, pic16lf1526 only figure 26-16: i dd maximum, external clock (ech), high-power mode, pic16lf1526 only 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 333 pic16(l)f1526/7 figure 26-17: i dd typical, external clock (ech), high-power mode, pic16f1526/7 only figure 26-18: i dd maximum, external clock (ech), high-power mode, pic16f1526/7 only 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 334 ? 2011-2015 microchip technology inc. figure 26-19: i dd , lfintosc, f osc = 31 khz, pic16lf1526 only figure 26-20: i dd , lfintosc, f osc = 31 khz, pic16f1526/7 only typical max. 0 5 10 15 20 25 30 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 5 10 15 20 25 30 35 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 335 pic16(l)f1526/7 figure 26-21: i dd , mfintosc, f osc = 500 khz, pic16lf1526 only figure 26-22: i dd , mfintosc, f osc = 500 khz, pic16f1526/7 only typical max. 100 150 200 250 300 350 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 100 150 200 250 300 350 400 450 500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 336 ? 2011-2015 microchip technology inc. figure 26-23: i dd typical, hfintosc, pic16lf1526 only figure 26-24: i dd maximum, hfintosc, pic16lf1526 only 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 337 pic16(l)f1526/7 figure 26-25: i dd typical, hfintosc, pic16f1526/7 only figure 26-26: i dd maximum, hfintosc, pic16f1526/7 only 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 338 ? 2011-2015 microchip technology inc. figure 26-27: i dd typical, hs oscillator, pic16lf1526 only figure 26-28: i dd maximum, hs oscillator, pic16lf1526 only 20 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c 20 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 339 pic16(l)f1526/7 figure 26-29: i dd typical, hs oscillator, pic16f1526/7 only figure 26-30: i dd maximum, hs oscillator, pic16f1526/7 only 20 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 20 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 340 ? 2011-2015 microchip technology inc. figure 26-31: i pd base, sleep mode, pic16lf1526 only figure 26-32: i pd base, low-power sleep mode, vregpm = 1 , pic16f1526/7 only 450 m85 c3 max. 250 300 350 400 450 d (na) max: 85c + 3 1 typical: 25c typical 0 50 100 150 200 250 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd (na) 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) max. 600 max. 300 400 500 600 p d (na) max: 85c + 3 1 typical: 25c typical 0 100 200 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 341 pic16(l)f1526/7 figure 26-33: i pd , watchdog timer (wdt), pic16lf1526 only figure 26-34: i pd , watchdog timer (wdt), pic16f1526/7 only 1.4 typical max. 0.6 0.8 1.0 1.2 1.4 i pd (a) max: 85c + 3 1 typical: 25c typical 0.0 0.2 0.4 0.6 08 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 1.2 typical max. 0.6 0.8 1.0 1.2 i pd ( a) max: 85c + 3 1 typical: 25c typical 0.0 0.2 0.4 0.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 342 ? 2011-2015 microchip technology inc. figure 26-35: i pd , fixed voltage reference (fvr), pic16lf1526 only figure 26-36: i pd , fixed voltage reference (fvr), pic16f1526/7 only max. 25 typical max. 10 15 20 25 i pd ( a) 0 5 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a max: 85c + 3 1 typical: 25c 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 30 typical max. 15 20 25 30 i pd ( a) 0 5 10 15 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( max: 85c + 3 1 typical: 25c 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 343 pic16(l)f1526/7 figure 26-37: i pd , brown-out reset (bor), borv = 1 , pic16lf1526 only figure 26-38: i pd , brown-out reset (bor), borv = 1 , pic16f1526/7 only 12 typical max. 6 8 10 12 d ( a) max: 85c + 3 1 typical: 25c 0 2 4 6 16 18 20 22 24 26 28 30 32 34 36 38 i pd ( a) 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) max 14 ma 85 c+3 1 typical max. 6 8 10 12 14 i pd ( a) max: 85c + 3 1 typical: 25c 0 2 4 6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a ) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 344 ? 2011-2015 microchip technology inc. figure 26-39: i pd , secondary oscillator, f osc = 32 khz, pic16lf1526 only figure 26-40: i pd , secondary oscillator, f osc = 32 khz, pic16f1526/7 only 6.0 t yp ical max. 3.0 4.0 5.0 6.0 i pd ( a) max: 85c + 3 1 typical: 25c typical 0.0 1.0 2.0 3.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 12 typical max. 6 8 10 12 i pd ( a) max: 85c + 3 1 typical: 25c typical 0 2 4 6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 345 pic16(l)f1526/7 figure 26-41: v oh vs. i oh over temperature, v dd = 5.5v, pic16f1526/7 only figure 26-42: v ol vs. i ol over temperature, v dd = 5.5v, pic16f1526/7 only -40c typical 125c 0 1 2 3 4 5 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 v oh (v) i oh (ma) graph represents 3 1 limits -40c typical 125c 0 1 2 3 4 5 0 1 02 03 04 05 06 07 08 09 01 0 0 v ol (v) i ol (ma) graph represents 3 1 limits downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 346 ? 2011-2015 microchip technology inc. figure 26-43: v oh vs. i oh over temperature, v dd = 3.0v figure 26-44: v ol vs. i ol over temperature, v dd = 3.0v -40c typical 125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 - 1 5- 1 3- 1 1- 9- 7- 5- 3- 1 v oh (v) i oh (ma) graph represents 3 1 limits -40c typical 125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 v ol (v) i ol (ma) graph represents 3 1 limits downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 347 pic16(l)f1526/7 figure 26-45: v oh vs. i oh over temperature, v dd = 1.8v, pic16lf1526 only figure 26-46: v ol vs. i ol over temperature, v dd = 1.8v, pic16lf1526 only -40c typical 125c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 v oh (v) i oh (ma) graph represents 3 1 limits -40c typical 125c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 01234567891 0 v ol (v) i ol (ma) graph represents 3 1 limits downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 348 ? 2011-2015 microchip technology inc. figure 26-47: por release voltage figure 26-48: por rearm voltage, pic16f1526/7 only typical max. min. 1.50 1.52 1.54 1.56 1.58 1.60 1.62 1.64 1.66 1.68 1.70 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1 typical max. min. 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 349 pic16(l)f1526/7 figure 26-49: brown-out reset voltage, borv = 1 , pic16lf1526 only figure 26-50: brown-out reset hysteresis, borv = 1 , pic16lf1526 only typical max. min. 1.80 1.85 1.90 1.95 2.00 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 10 20 30 40 50 60 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 350 ? 2011-2015 microchip technology inc. figure 26-51: brown-out reset voltage, borv = 1 , pic16f1526/7 only figure 26-52: brown-out reset hysteresis, borv = 1 , pic16f1526/7 only typical max. min. 2.30 2.35 2.40 2.45 2.50 2.55 2.60 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 10 20 30 40 50 60 70 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 351 pic16(l)f1526/7 figure 26-53: brown-out reset voltage, borv = 0 figure 26-54: brown-out reset hysteresis, borv = 0 typical max. min. 2.55 2.60 2.65 2.70 2.75 2.80 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 10 20 30 40 50 60 70 80 90 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 352 ? 2011-2015 microchip technology inc. figure 26-55: low-power brown-out reset voltage, lpbor = 0 figure 26-56: low-power brown-out reset hysteresis, lpbor = 0 typical max. min. 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 5 10 15 20 25 30 35 40 45 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1 downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 353 pic16(l)f1526/7 figure 26-57: wdt time-out period figure 26-58: pwrt period typical max. min. 10 12 14 16 18 20 22 24 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ms) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c) typical max. min. 40 50 60 70 80 90 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ms) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 354 ? 2011-2015 microchip technology inc. figure 26-59: fvr stabilization period typical max. 0 5 10 15 20 25 30 35 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 time (us) v dd (v) max: typical + 3 1 typical: statistical mean @ 25c note: the fvr stabilization period applies when: 1) coming out of reset or exiting sleep mode for pic12/16lfxxxx devices. 2) when exiting sleep mode with vregpm = 1 for pic12/16fxxxx devices in all other cases, the fvr is stable when released from reset. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 355 pic16(l)f1526/7 figure 26-60: lfintosc frequency over v dd and temperature, pic16lf1526 only figure 26-61: lfintosc frequency over v dd and temperature, pic16f1526/7 only typical max. min. 20 22 24 26 28 30 32 34 36 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 frequency (khz) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c) typical max. min. 20 22 24 26 28 30 32 34 36 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 frequency (khz) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c) downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 356 ? 2011-2015 microchip technology inc. figure 26-62: sleep mode, wake period with hfintosc source, pic16lf1526/7 only typical max. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 time (us) v dd (v) max: 85c + 3 1 typical: 25c downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 357 pic16(l)f1526/7 figure 26-63: low-power sleep mode, wake period with hfintosc source, vregpm = 1 , pic16f1526/7 only figure 26-64: sleep mode, wake period with hfintosc source, vregpm = 0 , pic16f1526/7 only typical max. 0 5 10 15 20 25 30 35 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (us) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 2 4 6 8 10 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (us) v dd (v) max: 85c + 3 1 typical: 25c downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 358 ? 2011-2015 microchip technology inc. 27.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: integrated development environment - mplab ? x ide software compilers/assemblers/linkers - mplab xc compiler -mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families simulators - mplab x sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 device programmers - mplab pm3 device programmer low-cost demonstration/development boards, evaluation kits and starter kits third-party development tools 27.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: color syntax highlighting smart code completion makes suggestions and provides hints as you type automatic code formatting based on user-defined rules live parsing user-friendly, customizable interface: fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. call graph window project-based workspaces: multiple projects multiple tools multiple configurations simultaneous debugging sessions file history and bug tracking: local file history feature built-in support for bugzilla issue tracker downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 359 pic16(l)f1526/7 27.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchips 8, 16, and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo- catable object files and archives to create an execut- able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem- bler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility 27.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: integration into mplab x ide projects user-defined macros to streamline assembly code conditional assembly for multipurpose source files directives that allow complete control over the assembly process 27.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 360 ? 2011-2015 microchip technology inc. 27.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 27.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 27.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchips most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineers pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 27.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineers pc using a full- speed usb interface and can be connected to the tar- get via a microchip debug (rj-11) connector (compati- ble with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 27.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications. downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 361 pic16(l)f1526/7 27.11 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 27.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. device programmers and gang programmers from companies, such as softlog and ccs software tools from companies, such as gimpel and trace systems protocol analyzers from companies, such as saleae and total phase demonstration boards from companies, such as mikroelektronika, digilent ? and olimex embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ? downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 362 ? 2011-2015 microchip technology inc. 28.0 packaging information 28.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec ? designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 64-lead tqfp (10x10x1 mm) example xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx pic16lf1527 -e/pt 1527017 3 e 64-lead qfn (9x9x0.9 mm) example pin 1 xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx yywwnnn pin 1 pic16lf1527 -e/mr 1527017 3 e downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 363 pic16(l)f1526/7 28.2 package details the following sections give the technical details of the packages. 0.20 c a-b d 64 x b 0.08 c a-b d c seating plane 4x n/4 tips top view side view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-085c sheet 1 of 2 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] d e e1 d1 d a b 0.20 h a-b d 4x d1/2 e a 0.08 c a1 a2 see detail 1 a a e1/2 note 1 note 2 1 2 3 n 0.05 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 364 ? 2011-2015 microchip technology inc. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] 13 12 11 e mold draft angle bottom 13 12 11 d mold draft angle top 0.27 0.22 0.17 b lead width 0.20 - 0.09 c lead thickness 10.00 bsc d1 molded package length 10.00 bsc e1 molded package width 12.00 bsc d overall length 12.00 bsc e overall width 7 3.5 0 i foot angle 0.75 0.60 0.45 l foot length 0.15 - 0.05 a1 standoff 1.05 1.00 0.95 a2 molded package thickness 1.20 - - a overall height 0.50 bsc e lead pitch 64 n number of leads max nom min dimension limits millimeters units footprint l1 1.00 ref 2. chamfers at corners are optional; size may vary. 1. pin 1 visual index feature may vary, but must be located within the hatched area. 4. dimensioning and tolerancing per asme y14.5m bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25mm per side. noes: microchip technology drawing c04-085c sheet 2 of 2 l (l1) e c h x x=a?b or d e/2 detail 1 section a-a t downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 365 pic16(l)f1526/7 recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: dimension limits units c1 contact pad spacing contact pad spacing contact pitch c2 millimeters 0.50 bsc min e max 11.4011.40 contact pad length (x28) contact pad width (x28) y1 x1 1.50 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technology drawing c04-2085b sheet 1 of 1 g distance between pads 0.20 nom 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] c2 c1 e g y1 x1 downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 366 ? 2011-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 367 pic16(l)f1526/7 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 368 ? 2011-2015 microchip technology inc. for the most current package drawin gs, please see the microchip packaging specification located at http://www.microchip.com/packaging note: downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 369 pic16(l)f1526/7 appendix a: data sheet revision history revision a (01/2011) original release. revision b (05/2011) electrical spec updates. revision c (01/2013) updated electrical spec and added characterization data graphs. revision d (09/2015) updated chapters high-performance risc cpu, device overview, memory organization, device configuration, enhanced universal synchronous asynchronous receiver transmitter (eusart), packaging information. other minor corrections. downloaded from: http:///
pic16(l)f1526/7 ds40001458d-page 370 ? 2011-2015 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f1526, pic16lf1526 pic16f1527, pic16lf1527 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= - 4 0 ? c to +85 ? c(industrial) e= - 4 0 ? c to +125 ? c (extended) package: (2) mr = plastic quad flat, no lead (qfn) pt = plastic thin quad flatpack (tqfp) pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16f1526t - i/mr 301 tape and reel, industrial temperature, qfn package, qtp pattern #301 b) pic16f1527 - i/pt industrial temperature tqfp package c) pic16f1527 - e/mr extended temperature, qfn package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: small form-factor packaging options may be available. please check www.microchip.com/packaging for small- form factor package availability, or contact your local sales office. [x] (1) tape and reel option - downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 371 pic16(l)f1526/7 the microchip web site microchip provides online support via our web site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://www.microchip.com/support downloaded from: http:///
ds40001458d-page 372 ? 2011-2015 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2011-2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-823-9 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market t oday, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
? 2011-2015 microchip technology inc. ds40001458d-page 373 americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 07/14/15 downloaded from: http:///

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